The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-5
ID121610 Non-Confidential
SMLABB, SMLABT,
SMLATB, SMLATT
Rd, Rn, Rm, Ra
Signed Multiply Accumulate Long (halfwords) Q page 3-79
SMLAD
,
SMLADX Rd, Rn, Rm, Ra
Signed Multiply Accumulate Dual Q page 3-81
SMLAL RdLo, RdHi, Rn, Rm
Signed Multiply with Accumulate (32 x 32 + 64), 64-bit
result
- page 3-93
SMLALBB, SMLALBT,
SMLALTB, SMLALTT
RdLo, RdHi, Rn, Rm
Signed Multiply Accumulate Long, halfwords - page 3-82
SMLALD
,
SMLALDX RdLo, RdHi, Rn, Rm
Signed Multiply Accumulate Long Dual - page 3-82
SMLAWB, SMLAWT Rd, Rn, Rm, Ra
Signed Multiply Accumulate, word by halfword Q page 3-79
SMLSD Rd, Rn, Rm, Ra
Signed Multiply Subtract Dual Q page 3-84
SMLSLD RdLo, RdHi, Rn, Rm
Signed Multiply Subtract Long Dual page 3-84
SMMLA Rd, Rn, Rm, Ra
Signed Most significant word Multiply Accumulate - page 3-86
SMMLS
,
SMMLR Rd, Rn, Rm, Ra
Signed Most significant word Multiply Subtract - page 3-86
SMMUL, SMMULR {Rd,} Rn, Rm
Signed Most significant word Multiply - page 3-88
SMUAD {Rd,} Rn, Rm
Signed dual Multiply Add Q page 3-89
SMULBB, SMULBT
SMULTB, SMULTT
{Rd,} Rn, Rm
Signed Multiply (halfwords) - page 3-91
SMULL RdLo, RdHi, Rn, Rm
Signed Multiply (32 x 32), 64-bit result - page 3-93
SMULWB, SMULWT {Rd,} Rn, Rm
Signed Multiply word by halfword - page 3-91
SMUSD
,
SMUSDX {Rd,} Rn, Rm
Signed dual Multiply Subtract - page 3-89
SSAT Rd, #n, Rm {,shift #s}
Signed Saturate Q page 3-96
SSAT16 Rd, #n, Rm
Signed Saturate 16 Q page 3-97
SSAX {Rd,} Rn, Rm
Signed Subtract and Add with Exchange GE page 3-60
SSUB16 {Rd,} Rn, Rm
Signed Subtract 16 - page 3-59
SSUB8 {Rd,} Rn, Rm
Signed Subtract 8 - page 3-59
STM Rn{!}, reglist
Store Multiple registers, increment after - page 3-32
STMDB, STMEA Rn{!}, reglist
Store Multiple registers, decrement before - page 3-32
STMFD, STMIA Rn{!}, reglist
Store Multiple registers, increment after - page 3-32
STR Rt, [Rn, #offset]
Store Register word - page 3-22
STRB, STRBT Rt, [Rn, #offset]
Store Register byte - page 3-22
STRD Rt, Rt2, [Rn, #offset]
Store Register two words - page 3-24
STREX Rd, Rt, [Rn, #offset]
Store Register Exclusive - page 3-36
STREXB Rd, Rt, [Rn]
Store Register Exclusive Byte - page 3-36
STREXH Rd, Rt, [Rn]
Store Register Exclusive Halfword - page 3-36
Table 3-1 Cortex-M4 instructions (continued)
Mnemonic Operands Brief description Flags Page
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