Revision history RM0008
1113/1128 DocID13902 Rev 15
23-Apr-2010 11
XL-density devices added.
Flash access control register (FLASH_ACR) inserted.
External source (HSE bypass) and External source (HSE bypass) : maximum HSE
frequency modified.
HSEBYP bit description modified in Section 7.3.1: Clock control register (RCC_CR) and
Section 8.3.1: Clock control register (RCC_CR).
SPI3_REMAP definition modified in Section 9.4.2: AF remap and debug I/O
configuration register (AFIO_MAPR).
Figure 48: DMA block diagram in connectivity line devices modified.
Figure 85: Center-aligned PWM waveforms (ARR=8) modified.
OIS1N and OIS1 bit descriptions modified in Section 14.4.2: TIM1&TIM8 control register
2 (TIMx_CR2).
FSMC block diagram reinserted.
Figure 202: Synchronous multiplexed read mode - NOR, PSRAM (CRAM) modified.
FSMC_ECCR2 and FSMC_ECCR3 reset value modified in Table 136: FSMC register
map.
Updated I2C Master mode Slave address transmission on page 750
Notes modified in the bit 5 descriptions in OTG_FS core interrupt register
(OTG_FS_GINTSTS) and OTG_FS interrupt mask register (OTG_FS_GINTMSK).
Transmission using DMA updated.
23-Apr-2010
11
continued
Updated Section 21: Flexible static memory controller (FSMC),
Updated Section 21.3: AHB interface on page 500
Updated Wrap support for NOR Flash/PSRAM on page 503
Added ASYNCWAIT, in Table 109: FSMC_BCRx bit fields on page 510
Added section WAIT management in asynchronous accesses on page 523
Updated Figure 200: Asynchronous wait during a write access on page 525
Updated Table 132: 16-bit PC Card on page 540
Added Section 21.6.7: PC Card/CompactFlash operations on page 545
Removed OTG_FS controller block diagram
Update Section 28.11.2: Peripheral Tx FIFOs
Added Section 28.13: FIFO RAM allocation
Updated Table 201: Core global control and status registers (CSRs)
Added method 1 and 2 in Section 26.3.3: I2C master mode
Updated note in POS bit description Section 26.6: I2C registers
Removed NPTXRWEN bit in Section 28: USB on-the-go full-speed (OTG_FS)
Updated formula for TRDT bit in Section 28: USB on-the-go full-speed (OTG_FS)
Removed BIM and TXFURM bits OTG_FS device IN endpoint common interrupt mask
register (OTG_FS_DIEPMSK)
Removed BOIM, OPEM, B2BSTUP bits in OTG_FS device OUT endpoint common
interrupt mask register (OTG_FS_DOEPMSK)
Updated Section : JTAG ID code on page 1077
Table 235. Document revision history (continued)
Date Revision Changes
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