DocID13902 Rev 15 1112/1128
RM0008 Revision history
1120
04-Dec-
2009
10
continued
TXFELVL bit description modified in OTG_FS AHB configuration register
(OTG_FS_GAHBCFG).
NPTXFE bit description modified in OTG_FS core interrupt register
(OTG_FS_GINTSTS).
NPTXFEM bit description modified in OTG_FS interrupt mask register
(OTG_FS_GINTMSK).
Figure 312: Transmit FIFO write task modified.
Bit 22 is reserved in OTG_FS interrupt mask register (OTG_FS_GINTMSK).
Bit 29 description modified in OTG device endpoint-x control register
(OTG_FS_DIEPCTLx) (x = 1..3, where x = Endpoint_number).
Bits 21:20 no longer reserved in OTG_FS Host channel-x characteristics register
(OTG_FS_HCCHARx) (x = 0..7, where x = Channel_number).
There are only 4 IN and OUT endpoints:
– Bit descriptions corrected in OTG_FS all endpoints interrupt mask register
(OTG_FS_DAINTMSK).
– Bits 15:0 description corrected in OTG_FS device IN endpoint FIFO empty interrupt
mask register: (OTG_FS_DIEPEMPMSK) (there are only 4 endpoints).
– Table 207: OTG_FS register map and reset values corrected
Note added to Section 29.4: Ethernet functional description: SMI, MII and RMII on
page 962.
Note added to Unicast destination address filter and Multicast destination address filter.
System consideration during power-down on page 993 updated.
Figure 326: ETH block diagram modified. CIC bit description modified in TDES0:
Transmit descriptor Word0 and TDES0: Transmit descriptor Word0: Transmit time stamp
control and status on page 967.
Ethernet MAC hash table high register (ETH_MACHTHR) description clarified.
Description of bits 6:2 modified in Ethernet DMA bus mode register (ETH_DMABMR).
Peripheral register access specified in Section 29.8: Ethernet register descriptions.
Table 235. Document revision history (continued)
Date Revision Changes
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