DocID13902 Rev 15 1118/1128
RM0008 Revision history
1120
02-Jun-
2014
15
(continued)
TIMER 2 to 5:
Removed all mentions to “repetition counter”.
Renamed Figure 113: Counter timing diagram, Update event. Updated Figure 127:
Output stage of capture/compare channel (channel 1).
Updated Figure 140: Master/Slave timer example to change ITR1 to ITR0. Updated
Section : Starting 2 timers synchronously in response to an external trigger
Updated read and write access to registers in Section 15.4: TIMx2 to TIM5 registers.
Removed note 1 related to OC1M bits and replaced IC2S by CC2S in Section 15.4.7:
TIMx capture/compare mode register 1 (TIMx_CCMR1).
TIMER9 to 14:
Removed TRGO output for timer controller in Figure 147: General-purpose timer block
diagram (TIM10/11/13/14).
Updated 16-bit prescaler range in Section 16.2: TIM9 to TIM14 main features.
Added register access in Section 16.4: TIM9 and TIM12 registers and Section 16.5:
TIM10/11/13/14 registers.
TIMER 16/17:
Removed references to repetition counter. Updated 16-bit prescaler factor in
Section 17.2: TIM6&TIM7 main features.Updated read/write access to registers in
Section 17.4: TIM6&TIM7 registers.
IWDG:
Corrected Figure 182: Independent watchdog block diagram..
Added register access in Section 19.4: IWDG registers.
WWDG:
Added register access in Section 20.6: WWDG registers
Table 235. Document revision history (continued)
Date Revision Changes
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