ST STM32F101 series Reference Manual

Revision history RM0008
1117/1128 DocID13902 Rev 15
02-Jun-
2014
15
Updated Table 3: Register boundary addresses
Restricted hyperlinks to homepages.
PWR:
Added note related to HSE failure in Section : Entering Stop mode. Updated note related
to Stop mode entry in Table 14: Stop mode. Changed conditions to clear CWUF in
Section 5.4.2: Power control/status register (PWR_CSR).
Low-, medium-, high- and XL-density RCC:
Updated Figure 7: Simplified diagram of the reset circuit.
Connectivity line RCC:
Updated Figure 10: Simplified diagram of the reset circuit.
Interrupts and events:
Updated bit definitions in Section 10.3.5: Software interrupt event register
(EXTI_SWIER) and Section 10.3.6: Pending register (EXTI_PR).
ADC:
Updated examples in Section 11.3.10: Discontinuous mode
Updated note related to prerequisites to start calibration in Section 11.4: Calibration.
Updated note related to sampling time in Section 11.9.1: Injected simultaneous mode,
Section 11.9.2: Regular simultaneous mode, Section 11.9.7: Combined regular/injected
simultaneous mode, and Section 11.9.8: Combined regular simultaneous + alternate
trigger mode.
TIMER1/8:
Updated 16-bit prescaler range in Section 14.2: TIM1&TIM8 main features.
Modified update event generation in Upcounting mode and Downcounting mode in
Section 14.3.2: Counter modes, and in Section 14.3.3: Repetition counter.
Updated OC1 block diagram in Figure 80: Output stage of capture/compare channel
(channel 1 to 3). Updated Section 14.3.6: Input capture mode.
Updated bits that control the dead-time generation in Section 14.3.11:
Complementary outputs and dead-time insertion.
Updated ways to generate a break in Section 14.3.12: Using the break function.
OCxREF changed to ETR in the example given in Section 14.3.13: Clearing the
OCxREF signal on an external event and OCREF_CLR to ETRF in Figure 90: Clearing
TIMx OCxREF
.
Updated configuration for example of counter operation in encoder interface mode in
Section 14.3.16: Encoder interface mode.
Updated Section 14.3.18: Interfacing with Hall sensors.
Updated CCPC definition in Section 14.4.2: TIM1&TIM8 control register 2 (TIMx_CR2).
Changed definition of ARR[15:0] bits in Section 14.4.12: TIM1&TIM8 auto-reload
register (TIMx_ARR).
Updated BKE definition in Section 14.4.18: TIM1&TIM8 break and dead-time register
(TIMx_BDTR).
Table 235. Document revision history (continued)
Date Revision Changes

ST STM32F101 series Specifications

General

Brand	ST
Model	STM32F101 series
Category	Computer Hardware
Language	English