DocID13902 Rev 15 60/1128
RM0008 Memory and bus architecture
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used only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or
the HSE but not from the PLL.
The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB
clock.
The prefetch buffer must be switched on/off only when SYSCLK is lower than 24 MHz and
no prescaler is applied on the AHB clock (SYSCLK must be equal to HCLK). The prefetch
buffer is usually switched on/off during the initialization routine, while the microcontroller is
running on the internal 8 MHz RC (HSI) oscillator.
Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode
instructions. The DMA provides one free cycle after each transfer. Some instructions can be
performed together with DMA transfer.
Programming and erasing the Flash memory
The Flash memory can be programmed 16 bits (half words) at a time.
For write and erase operations on the Flash memory (write/erase), the internal RC oscillator
(HSI) must be ON.
The Flash memory erase operation can be performed at page level or on the whole Flash
area (mass-erase). The mass-erase does not affect the information blocks.
To ensure that there is no over-programming, the Flash Programming and Erase Controller
blocks are clocked by a fixed clock.
The End of write operation (programming or erasing) can trigger an interrupt. This interrupt
can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the
interrupt is served only after an exit from WFI.
The FLASH_ACR register is used to enable/disable prefetch and half cycle access, and to
control the Flash memory access time according to the CPU frequency. The tables below
provide the bit map and bit descriptions for this register.
For complete information on Flash memory operations and register configurations, please
refer to the STM32F10xxx Flash programming manual (PM0075) or to the XL
STM32F10xxx Flash programming manual (PM0068).
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