STMicroelectronics STM32F405 User Manual

Embedded Flash memory interface RM0090
102/1731 DocID018909 Rev 11
3.9.6 Flash status register (FLASH_SR) for
STM32F42xxx and STM32F43xxx
The Flash status register gives information on ongoing program and erase operations.
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Bits 3:2 Reserved, must be kept cleared.
Bit 1 OPERR: Operation error
Set by hardware when a flash operation (programming / erase /read) request is detected and
can not be run because of parallelism, alignment, or write protection error. This bit is set only if
error interrupts are enabled (ERRIE = 1).
Bit 0 EOP: End of operation
Set by hardware when one or more Flash memory operations (program/erase) has/have
completed successfully. It is set only if the end of operation interrupts are enabled (EOPIE = 1).
Cleared by writing a 1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
RDERR PGSERR PGPERR PGAERR WRPERR
Reserved
OPERR EOP
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:17 Reserved, must be kept cleared.
Bit 16 BSY: Busy
This bit indicates that a Flash memory operation is in progress to/from one bank. It is set at the
beginning of a Flash memory operation and cleared when the operation finishes or an error
occurs.
0: no Flash memory operation ongoing
1: Flash memory operation ongoing
Bits 15:9 Reserved, must be kept cleared.
Bit 8 RDERR: Proprietary readout protection (PCROP) error
Set by hardware when a read access through the D-bus is performed to an address belonging
to a proprietary readout protected Flash sector.
Cleared by writing 1.
Bit 7 PGSERR: Programming sequence error
Set by hardware when a write access to the Flash memory is performed by the code while the
control register has not been correctly configured.
Cleared by writing 1.

STMicroelectronics STM32F405 Specifications

General

Brand	STMicroelectronics
Model	STM32F405
Category	Controller
Language	English