DocID018909 Rev 11 831/1731
RM0090 Inter-integrated circuit (I
2
C) interface
864
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is
always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to
Figure 238.
Figure 238. I
2
C bus protocol
Acknowledge may be enabled or disabled by software. The I
2
C interface addresses (dual
addressing 7-bit/ 10-bit and/or general call address) can be selected by software.
The block diagram of the I
2
C interface is shown in Figure 239.
SCL
SDA
12 8 9
MSB
ACK
Stop
Start
condition
condition
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