DocID018909 Rev 11 133/1731
RM0090 Power controller (PWR)
149
5.3.5 Stop mode (STM32F42xxx and STM32F43xxx)
The Stop mode is based on the Cortex
®
-M4 with FPU deepsleep mode combined with
peripheral clock gating. The voltage regulator can be configured either in normal or low-
power mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI
and the HSE RC oscillators are disabled. Internal SRAM and register contents are
preserved.
In Stop mode, the power consumption can be further reduced by using additional settings in
the PWR_CR register. However this will induce an additional startup delay when waking up
from Stop mode (see Table 28).
Mode exit
If WFI or Return from ISR was used for entry:
Any EXTI lines configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 61: Vector table for STM32F405xx/07xx and STM32F415xx/17xx
on page 374 and Table 62: Vector table for STM32F42xxx and
STM32F43xxx.
If WFE was used for entry and SEVONPEND = 0
Any EXTI lines configured in event mode. Refer to Section 12.2.3:
Wakeup event management on page 382.
If WFE was used for entry and SEVONPEND = 1:
– Any EXTI lines configured in Interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be an external interrupt or a peripheral with wakeup capability. Refer to
Table 61: Vector table for STM32F405xx/07xx and STM32F415xx/17xx
on page 374 and Table 62: Vector table for STM32F42xxx and
STM32F43xxx.
– Wakeup event: refer to Section 12.2.3: Wakeup event management on
page 382.
Wakeup latency
Table 26: Stop operating modes (STM32F405xx/07xx and
STM32F415xx/17xx)
Table 27. Stop mode entry and exit (for STM32F405xx/07xx and STM32F415xx/17xx)
Stop mode Description
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