STMicroelectronics STM32F405 User Manual

DocID018909 Rev 11 1327/1731
RM0090 USB on-the-go full-speed (OTG_FS)
1368
1. When an STALL, TXERR, BBERR or DTERR interrupt in OTG_FS_HCINTx is received
for an IN or OUT channel. The application must be able to receive other interrupts
(DTERR, Nak, Data, TXERR) for the same channel before receiving the halt.
2. When a DISCINT (Disconnect Device) interrupt in OTG_FS_GINTSTS is received.
(The application is expected to disable all enabled channels).
3. When the application aborts a transfer before normal completion.
Operational model
The application must initialize a channel before communicating to the connected device.
This section explains the sequence of operation to be performed for different types of USB
transactions.
• Writing the transmit FIFO
The OTG_FS host automatically writes an entry (OUT request) to the periodic/non-
periodic request queue, along with the last DWORD write of a packet. The application
must ensure that at least one free space is available in the periodic/non-periodic
request queue before starting to write to the transmit FIFO. The application must
always write to the transmit FIFO in DWORDs. If the packet size is non-DWORD
aligned, the application must use padding. The OTG_FS host determines the actual
packet size based on the programmed maximum packet size and transfer size.
Figure 396. Transmit FIFO write task
MPS: Maximum packet size
Start
ai15673b
Wait for NPTXFE/PTXFE
interrupt in
OTG_FS_GINTSTS
Read GNPTXSTS/HPTXFSIZ
registers for available FIFO
and queue spaces
1 MPS or
LPS FIFO space
available?
Write 1 packet
data to
transmit FIFO
More packets
to send?
Done
No
No
Ye s
Ye s
LPS: Last packet size

STMicroelectronics STM32F405 Specifications

General

Brand	STMicroelectronics
Model	STM32F405
Category	Controller
Language	English