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STMicroelectronics STM32F405 User Manual

STMicroelectronics STM32F405
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DocID018909 Rev 11 1433/1731
RM0090 USB on-the-go high-speed (OTG_HS)
1529
Table 209 contains the minimum duration (according to device state) for which the Soft
disconnect (SDIS) bit must be set for the USB host to detect a device disconnect. To
accommodate clock jitter, it is recommended that the application add some extra delay to
the specified minimum duration.
Bit 2 GINSTS: Global IN NAK status
0: A handshake is sent out based on the data availability in the transmit FIFO.
1: A NAK handshake is sent out on all nonperiodic IN endpoints, irrespective of the data
availability in the transmit FIFO.
Bit 1 SDIS: Soft disconnect
The application uses this bit to signal the USB OTG core to perform a soft disconnect. As
long as this bit is set, the host does not see that the device is connected, and the device
does not receive signals on the USB. The core stays in the disconnected state until the
application clears this bit.
0: Normal operation. When this bit is cleared after a soft disconnect, the core generates a
device connect event to the USB host. When the device is reconnected, the USB host
restarts device enumeration.
1: The core generates a device disconnect event to the USB host.
Bit 0 RWUSIG: Remote wakeup signaling
When the application sets this bit, the core initiates remote signaling to wake up the USB
host. The application must set this bit to instruct the core to exit the Suspend state. As
specified in the USB 2.0 specification, the application must clear this bit 1 ms to 15 ms after
setting it.
Table 209. Minimum duration for soft disconnect
Operating speed Device state Minimum duration
High speed Not Idle or Suspended (Performing transactions) 125 µs
Full speed Suspended 1 ms + 2.5 µs
Full speed Idle 2.5 µs
Full speed Not Idle or Suspended (Performing transactions) 2.5 µs

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STMicroelectronics STM32F405 Specifications

General IconGeneral
BrandSTMicroelectronics
ModelSTM32F405
CategoryController
LanguageEnglish

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