DocID018909 Rev 11 1555/1731
RM0090 Flexible static memory controller (FSMC)
1588
WAIT management in asynchronous accesses
If the asynchronous memory asserts a WAIT signal to indicate that it is not yet ready to
accept or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase) programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET[3:0] and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
The data setup phase (DATAST in the FSMC_BTRx register) must be programmed so that
WAIT can be detected 4 HCLK cycles before the end of memory transaction. The following
cases must be considered:
1 MUXEN 0x1
0 MBKEN 0x1
Table 236. FSMC_BTRx bit fields
Bit No. Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x0
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST HCLK cycles for
read accesses and DATAST+1 HCLK cycles for write accesses).
7-4 ADDHLD Duration of the middle phase of the access (ADDHLD HCLK cycles).
3-0 ADDSET[3:0]
Duration of the first access phase (ADDSET HCLK cycles).
Minimum value for ADDSET is 1.
Table 235. FSMC_BCRx bit fields (continued)
Bit No. Bit name Value to set
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