Serial peripheral interface (SPI) RM0090
880/1731 DocID018909 Rev 11
Transmit-only procedure (BIDIMODE=0 RXONLY=0)
In this mode, the procedure can be reduced as described below and the BSY bit can be
used to wait until the completion of the transmission (see
Figure 255 and Figure 256).
1. Enable the SPI by setting the SPE bit to 1.
2. Write the first data item to send into the SPI_DR register (this clears the TXE bit).
3. Wait until TXE=1 and write the next data item to be transmitted. Repeat this step for
each data item to be transmitted.
4. After writing the last data item into the SPI_DR register, wait until TXE=1, then wait until
BSY=0, this indicates that the transmission of the last data is complete.
This procedure can be also implemented using dedicated interrupt subroutines launched at
each rising edge of the TXE flag.
Note: During discontinuous communications, there is a 2 APB clock period delay between the
write operation to SPI_DR and the BSY bit setting. As a consequence, in transmit-only
mode, it is mandatory to wait first until TXE is set and then until BSY is cleared after writing
the last data.
After transmitting two data items in transmit-only mode, the OVR flag is set in the SPI_SR
register since the received data are never read.
Figure 255. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in
case of continuous transfers
0xF1
Tx buffer
TXE flag
0xF2
BSY flag
0xF3
software writes
0xF1 into
SPI_DR
software waits
until TXE=1 and
writes 0xF2 into
SPI_DR
set by hardware
cleared by software
set by hardware
cleared by software
set by hardware
set by hardware
SCK
reset by hardware
Example in Master mode with CPOL=1, CPHA=1
(write to SPI_DR)
MISO/MOSI (out)
DATA 1 = 0xF1
DATA 2 = 0xF2
DATA 3 = 0xF3
software waits
until TXE=1 and
writes 0xF3 into
SPI_DR
software waits until BSY=0software waits until TXE=1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3 b4 b5 b6 b7
ai17345
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