STMicroelectronics STM32F405 User Manual

DocID018909 Rev 11 725/1731
RM0090 Cryptographic processor (CRYP)
757
Figure 227. AES-CTR mode decryption
1. K: key; C: cipher text; I: input Block; o: output block; Ps: plain text before swapping (when decoding) or
after swapping (when encoding); Cs: cipher text after swapping (when decoding) or before swapping (when
encoding); P: plain text; IV: Initialization vectors.
Figure 228 shows the structure of the IV block as defined by the standard [2]. It is composed
of three distinct fields.
Figure 228. Initial counter block structure for the Counter mode
• Nonce is a 32-bit, single-use value. A new nonce should be assigned to each different
communication.
• The initialization vector (IV) is a 64-bit value and the standard specifies that the
encryptor must choose IV so as to ensure that a given value is used only once for a
given key
• The counter is a 32-bit big-endian integer that is incremented each time a block has
been encrypted. The initial value of the counter should be set to ‘1’.
The block increments the least significant 32 bits, while it leaves the other (most significant)
96 bits unchanged.
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STMicroelectronics STM32F405 Specifications

General

Brand	STMicroelectronics
Model	STM32F405
Category	Controller
Language	English