STMicroelectronics STM32F405 User Manual

DocID018909 Rev 11 1597/1731
RM0090 Flexible memory controller (FMC)
1669
The HADDR[27:0] bits are translated to external SDRAM address depending on the
SDRAM controller configuration:
• Data size:8, 16 or 32 bits
• Row size:11, 12 or 13 bits
• Column size: 8, 9, 10 or 11 bits
• Number of internal banks: two or four internal banks
Table 255 to Table shows the SDRAM address mapping versus the SDRAM controller
configuration.
)
1. When interfacing with a 16-bit memory, the FMC internally uses the HADDR[11:1] internal AHB address
lines to generate the external address. When interfacing with a 32-bit memory, the FMC internally uses
HADDR[12:2] lines to generate the external address. Whatever the memory width, FMC_A[0] has to be
connected to the external memory address A[0].
2. The AutoPrecharge is not supported. FMC_A[10] must be connected to the external memory address
A[10] but it will be always driven ‘low’.
Table 255. SDRAM address mapping with 8-bit data bus width
(1)(2)
Row size
configuration
HADDR(AHB Internal Address Lines)
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11-bit row size
configuration
Res.
Bank
[1:0]
Row[10:0] Column[7:0]
Res.
Bank
[1:0]
Row[10:0] Column[8:0]
Res.
Bank
[1:0]
Row[10:0] Column[9:0]
Res.
Bank
[1:0]
Row[10:0] Column[10:0]
12-bit row size
configuration
Res.
Bank
[1:0]
Row[11:0] Column[7:0]
Res.
Bank
[1:0]
Row[11:0] Column[8:0]
Res.
Bank
[1:0]
Row[11:0] Column[9:0]
Res.
Bank
[1:0]
Row[11:0] Column[10:0]
13-bit row size
configuration
Res.
Bank
[1:0]
Row[12:0] Column[7:0]
Res.
Bank
[1:0]
Row[12:0] Column[8:0]
Res.
Bank
[1:0]
Row[12:0] Column[9:0]
Res.
Bank
[1:0]
Row[12:0] Column[10:0]
1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.
2. Access to Reserved (Res.) address range generates an AHB error.

STMicroelectronics STM32F405 Specifications

General

Brand	STMicroelectronics
Model	STM32F405
Category	Controller
Language	English