Chrom-Art Accelerator™ controller (DMA2D) RM0090
354/1731 DocID018909 Rev 11
11.5 DMA2D registers
11.5.1 DMA2D control register (DMA2D_CR)
Address offset: 0x0000
Reset value: 0x0000 0000
CLUT access error CAEIF CAEIE
Transfer watermark TWF TWIE
Transfer complete TCIF TCIE
Transfer error TEIF TEIE
Table 59. DMA2D interrupt requests (continued)
Interrupt event Event flag Enable control bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
MODE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CEIE CTCIE CAEIE TWIE TCIE TEIE
Reserved
ABORT SUSP START
rw rw rw rw rw rw rs rw rs
Bits 31:18 Reserved, must be kept at reset value
Bits 17:16 MODE: DMA2D mode
This bit is set and cleared by software. It cannot be modified while a transfer is ongoing.
00: Memory-to-memory (FG fetch only)
01: Memory-to-memory with PFC (FG fetch only with FG PFC active)
10: Memory-to-memory with blending (FG and BG fetch with PFC and blending)
11: Register-to-memory (no FG nor BG, only output stage active)
Bits 15:14 Reserved, must be kept at reset value
Bit 13 CEIE: Configuration Error Interrupt Enable
This bit is set and cleared by software.
0: CE interrupt disable
1: CE interrupt enable
Bit 12 CTCIE: CLUT transfer complete interrupt enable
This bit is set and cleared by software.
0: CTC interrupt disable
1: CTC interrupt enable
Bit 11 CAEIE: CLUT access error interrupt enable
This bit is set and cleared by software.
0: CAE interrupt disable
1: CAE interrupt enable
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