STMicroelectronics STM32F405 User Manual

DocID018909 Rev 11 953/1731
RM0090 Serial audio interface (SAI)
957
29.17.6 SAI xStatus register (SAI_xSR) where x is A or B
Address offset: block A: 0x018
Address offset: block B: 0x038
Reset value: 0x0000 0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
FLTH
rrr
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
LFSDET AFSDET CNRDY FREQ WCKCFG
MUTED
ET
OVRUDR
rr r r r rr
Bits 31:19 Reserved, always read as 0.
Bits 18:16 FLTH: FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by
hardware and its setting depends on SAI block configuration (transmitter or receiver mode).
If SAI block is configured as transmitter:
000: FIFO_empty
001: FIFO <= ¼ but not empty
010: ¼ < FIFO <= ½
011: ½ < FIFO <= ¾
100: ¾ < FIFO but not full
101: FIFO full
If SAI block is configured as receiver:
000: FIFO_empty
001: FIFO < ¼ but not empty
010: ¼ <= FIFO < ½
011: ½ =< FIFO < ¾
100: ¾ =< FIFO but not full
101: FIFO full
Bits 15:7 Reserved, always read as 0.
Bit 6 LFSDET: Late frame synchronization detection. This bit is read only.
0: No error.
1: Frame synchronization signal is not present at the right time.
This flag can be set only if the audio block is configured in Slave mode.
It is not used in AC’97 mode.
It may generate an interrupt if bit LFSDETIE in the SAI_xIM register is set.
This flag is cleared when the software sets bit CLFSDET in the SAI_xCLRFR register
Bit 5 AFSDET: Anticipated frame synchronization detection. This bit is read only.
0: No error.
1: Frame synchronization signal is detected earlier than expected.
This flag can be set only if the audio block is configured in Slave mode.
It is not used in AC’97.
It may generate an interrupt if bit AFSDETIE in the SAI_xIM register is set.
This flag is cleared when the software sets bit CAFSDET in the SAI_xCLRFR register

STMicroelectronics STM32F405 Specifications

General

Brand	STMicroelectronics
Model	STM32F405
Category	Controller
Language	English