Flexible memory controller (FMC) RM0090
1634/1731 DocID018909 Rev 11
37.6 NAND Flash/PC Card controller
The FMC generates the appropriate signal timings to drive the following types of device:
• 8- and 16-bit NAND Flash memories
• 16-bit PC Card compatible devices
The NAND Flash/PC Card controller can control three external banks, Bank 2, 3 and 4:
• Bank 2 and Bank 3 support NAND Flash devices
• Bank 4 supports PC Card devices.
Each bank is configured through dedicated registers (Section 37.6.8). The programmable
memory parameters include access timings (shown in Table 284) and ECC configuration.
Bits 15:8 DATAST[3:0]: Data-phase duration.
These bits are written by software to define the duration of the data phase (refer toFigure 456 to
Figure 468), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 × HCLK clock cycles
0000 0010: DATAST phase duration = 2 × HCLK clock cycles
...
1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
Bits 7:4 ADDHLD[3:0]: Address-hold phase duration.
These bits are written by software to define the duration of the address hold phase (refer to
Figure 465 to Figure 468), used in asynchronous multiplexed accesses:
0000: Reserved
0001: ADDHLD phase duration = 1 × HCLK clock cycle
0010: ADDHLD phase duration = 2 × HCLK clock cycle
...
1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always
1 Flash clock period duration.
Bits 3:0 ADDSET[3:0]: Address setup phase duration.
These bits are written by software to define the duration of the address setup phase in HCLK cycles
(refer to Figure 465 to Figure 468), used in asynchronous accesses:
0000: ADDSET phase duration = 0 × HCLK clock cycle
...
1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash and PSRAM accesses, this value is not used, the address setup
phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value
is 1.
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