DocID018909 Rev 11 965/1731
RM0090 Universal synchronous asynchronous receiver transmitter (USART)
1010
When a transmission is taking place, a write instruction to the USART_DR register stores
the data in the TDR register and which is copied in the shift register at the end of the current
transmission.
When no transmission is taking place, a write instruction to the USART_DR register places
the data directly in the shift register, the data transmission starts, and the TXE bit is
immediately set.
If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An
interrupt is generated if the TCIE bit is set in the USART_CR1 register.
After writing the last data into the USART_DR register, it is mandatory to wait for TC=1
before disabling the USART or causing the microcontroller to enter the low-power mode
(see
Figure 299: TC/TXE behavior when transmitting).
The TC bit is cleared by the following software sequence:
1. A read from the USART_SR register
2. A write to the USART_DR register
Note: The TC bit can also be cleared by writing a ‘0 to it. This clearing sequence is recommended
only for Multibuffer communication.
Figure 299. TC/TXE behavior when transmitting
Break characters
Setting the SBK bit transmits a break character. The break frame length depends on the M
bit (see
Figure 297).
If the SBK bit is set to ‘1 a break character is sent on the TX line after completing the current
character transmission. This bit is reset by hardware when the break character is completed
(during the stop bit of the break character). The USART inserts a logic 1 bit at the end of the
last break frame to guarantee the recognition of the start bit of the next frame.
Note: If the software resets the SBK bit before the commencement of break transmission, the
break character will not be transmitted. For two consecutive breaks, the SBK bit should be
set after the stop bit of the previous break.
Idle characters
Setting the TE bit drives the USART to send an idle frame before the first data frame.
TX line
USART_DR
Frame 1
TXE flag
F2
TC flag
F3
Frame 2
software waits until TXE=1
and writes F2 into DR
software waits until TXE=1
and writes F3 into DR
TC is not set
because TXE=0
software waits until TC=1
Frame 3
TC is set because
TXE=1
set by hardware
cleared by software
set by hardware
cleared by software
set by hardware
set
Idle preamble
by hardware
F1
software
enables the
USART
TC is not set
because TXE=0
software waits until TXE=1
and writes F1 into DR
ai17121b
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