Serial peripheral interface (SPI) RM0090
898/1731 DocID018909 Rev 11
Figure 274. LSB Justified 24-bit frame length with CPOL = 0
• In transmission mode:
If data 0x3478AE have to be transmitted, two write operations to the SPI_DR register
are required from software or by DMA. The operations are shown below.
Figure 275. Operations required to transmit 0x3478AE
• In reception mode:
If data 0x3478AE are received, two successive read operations from SPI_DR are
required on each RXNE event.
Figure 276. Operations required to receive 0x3478AE
CK
WS
SD
Channel left 32-bit
Channel right
MSB
LSB
24-bit remaining
0 forced
8-bit data
Transmission
Reception
0xXX34 0x78AE
First write to Data register
Second write to Data register
Only the 8 LSB bits of the half-word
are significant. Whatever the 8 MSBs
a field of 0x00 is forced instead
conditioned by TXE = ‘1’
conditioned by TXE = ‘1’
0x0034 0x78AE
First read from Data register
Second read from Data register
Only the 8 LSB bits of the half-word
are significant. Whatever the 8 MSBs,
a field of 0x00 is forced instead
conditioned by RXNE = ‘1’
conditioned by RXNE = ‘1’
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