DocID018909 Rev 11 633/1731
RM0090 General-purpose timers (TIM2 to TIM5)
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Note: The state of the external IO pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.
18.4.10 TIMx counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000 0000
18.4.11 TIMx prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
18.4.12 TIMx auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0x 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT[31:16] (depending on timers)
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
CNT[15:0]
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Bits 15:0 CNT[15:0]: Counter value
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
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Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR[31:16] (depending on timers)
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 18.3.1: Time-base unit on page 583 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.
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