STMicroelectronics STM32F405

DocID018909 Rev 11 343/1731
RM0090 Chrom-Art Accelerator™ controller (DMA2D)
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Figure 40. DMA2D block diagram
11.3.2 DMA2D control
The DMA2D controller is configured through the DMA2D Control Register (DMA2D_CR)
which allows selecting:
The user application can perform the following operations:
• Select the operating mode
• Enable/disable the DMA2D interrupt
• Start/suspend/abort ongoing data transfers
11.3.3 DMA2D foreground and background FIFOs
The DMA2D foreground (FG) FG FIFO and background (BG) FIFO fetch the input data to
be copied and/or processed.
The FIFOs fetch the pixels according to the color format defined in their respective pixel
format converter (PFC).
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