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DocID018909 Rev 11 781/1731

RM0090 Hash processor (HASH)

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25.4.5 HASH digest registers (HASH_HR0..4/5/6/7)

Address offset: 0x0C to 0x1C (STM32F415/417xx), plus 0x310 to 0x32C (STM32F43xxx)

Reset value: 0x0000 0000

These registers contain the message digest result named as:

1. H0, H1, H2, H3 and H4, respectively, in the SHA1 algorithm description

Note that in this case, the HASH_H5 to HASH_H7 register is not used, and is read as

zero.

2. A, B, C and D, respectively, in the MD5 algorithm description

Note that in this case, the HASH_H4 to HASH_H7 register is not used, and is read as

zero.

3. H0 to H6, respectively, in the SHA224 algorithm description,

Note that in this case, the HASH_H7 register is not used, and is read as zero.

4. H0 to H7, respectively, in the SHA256 algorithm description,

If a read access to one of these registers occurs while the HASH core is calculating an

intermediate digest or a final message digest (that is when the DCAL bit has been written to

1), then the read is stalled until the completion of the HASH calculation.

Note: H0, H1, H2, H3 and H4 mapping are duplicated in two region.

HASH_HR0

Address offset: 0x0C and 0x310

HASH_HR1

Address offset: 0x10 and 0x314

HASH_HR2

Address offset: 0x14 and 0x318

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STMicroelectronics STM32F405 User Manual

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