DocID018909 Rev 11 841/1731
RM0090 Inter-integrated circuit (I
2
C) interface
864
Figure 244. Transfer sequence diagram for master receiver
1. If a single byte is received, it is NA.
2. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence.
3. The EV7 event stretches SCL low if the software sequence is not completed before the end of the next byte
reception.
4. The EV7_1 software sequence must be completed before the ACK pulse of the current byte transfer.
The procedures described below are recommended if the EV7-1 software sequence is not
completed before the ACK pulse of the current byte transfer.
These procedures must be followed to make sure:
• The ACK bit is set low on time before the end of the last data reception
• The STOP bit is set high after the last data reception without reception of
supplementary data.
For 2-byte reception:
• Wait until ADDR = 1 (SCL stretched low until the ADDR flag is cleared)
• Set ACK low, set POS high
• Clear ADDR flag
• Wait until BTF = 1 (Data 1 in DR, Data2 in shift register, SCL stretched low until a data
1 is read)
• Set STOP high
• Read data 1 and 2
BITMASTERRECEIVER
BITMASTERRECEIVER
,EGEND33TART3
R
2EPEATED3TART03TOP!!CKNOWLEDGE.!.ONACKNOWLEDGE
%6X%VENTWITHINTERRUPTIF)4%6&%.
%63"CLEAREDBYREADING32REGISTERFOLLOWEDBYWRITING$2REGISTER
%6!$$2CLEAREDBYREADING32REGISTERFOLLOWEDBYREADING32)NBITMASTERRECEIVERMODETHISSE
QUENCESHOULDBEFOLLOWEDBYWRITING#2WITH34!24
%62X.%CLEAREDBYREADING$2REGISTER
%6?2X.%CLEAREDBYREADING$2REGISTERPROGRAM!#+AND34/0REQUEST
%6!$$CLEAREDBYREADING32REGISTERFOLLOWEDBYWRITING$2REGISTER
3 !DDRESS ! $ATA !
$ATA !
$ATA. .! 0
%6 %6 %6 %6 %6? %6
3 (EADER ! !DDRESS !
%6 %6 %6
3
R
(EADER !
$ATA !
%6
%6 %6
$ATA !
%6
$ATA. .! 0
%6? %6
AID
)NCASEOFTHERECEPTIONOFBYTETHE!CKNOWLEDGEDISABLEMUSTBEPERFORMEDDURING%6EVENTIEBEFORECLEARING!$$2FLAG
To Next Page
Loading...
Need help?
General
