STMicroelectronics STM32F405 User Manual

Ethernet (ETH): media access control (MAC) with DMA controller RM0090
1162/1731 DocID018909 Rev 11
Figure 378. TxDMA operation in OSF mode
Transmit frame processing
The transmit DMA expects that the data buffers contain complete Ethernet frames,
excluding preamble, pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain
valid data. If the transmit descriptor indicates that the MAC core must disable CRC or pad
insertion, the buffer must have complete Ethernet frames (excluding preamble), including
the CRC bytes. Frames can be data-chained and span over several buffers. Frames have to
be delimited by the first descriptor (TDES0[28]) and the last descriptor (TDES0[29]). As the
transmission starts, TDES0[28] has to be set in the first descriptor. When this occurs, the
frame data are transferred from the memory buffer to the Transmit FIFO. Concurrently, if the
last descriptor (TDES0[29]) of the current frame is cleared, the transmit process attempts to
acquire the next descriptor. The transmit process expects TDES0[28] to be cleared in this
descriptor. If TDES0[29] is cleared, it indicates an intermediary buffer. If TDES0[29] is set, it
Previous frame
status available
Start TxDMA
(Re-)fetch next
descriptor
Write status word to
prev. frame’s TDES0
Transfer data from
buffer(s)
(AHB)
error?
Own
bit set?
(AHB)
error?
Frame xfer
complete?
Time stamp
present?
(AHB)
error?
Write time stamp to
TDES2 & TDES3
for previous frame
(AHB)
error?
Stop TxDMA
No
Ye s
No
Ye s
No
Start
Ye s
Close intermediate
descriptor
No
No
Wait for previous
frame’s Tx status
Second
frame?
Ye s
Ye s
No
Ye s
Ye s
Write time stamp to
TDES2 & TDES3
for previous frame
(AHB)
error?
(AHB)
error?
Ye s
Time stamp
present?
Ye s
Write status word to
prev. frame’s TDES0
TxDMA suspended
Ye s
No
Ye s
No
No
Poll
demand
No
No
ai15640

STMicroelectronics STM32F405 Specifications

General

Brand	STMicroelectronics
Model	STM32F405
Category	Controller
Language	English