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RM0090 Interrupts and events
389
12 Interrupts and events
This Section applies to the whole STM32F4xx family, unless otherwise specified.
12.1 Nested vectored interrupt controller (NVIC)
12.1.1 NVIC features
The nested vector interrupt controller NVIC includes the following features:
• 82 maskable interrupt channels for STM32F405xx/07xx and STM32F415xx/17xx, and
up to 91 maskable interrupt channels for STM32F42xxx and STM32F43xxx (not
including the 16 interrupt lines of Cortex
®
-M4 with FPU)
• 16 programmable priority levels (4 bits of interrupt priority are used)
• low-latency exception and interrupt handling
• power management control
• implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to programming manual PM0214.
12.1.2 SysTick calibration value register
The SysTick calibration value is fixed to 18750, which gives a reference time base of 1 ms
with the SysTick clock set to 18.75 MHz (HCLK/8, with HCLK set to 150 MHz).
12.1.3 Interrupt and exception vectors
See Table 62 and Table 62 , for the vector table for the STM32F405xx/07xx and
STM32F415xx/17xx and STM32F42xxx and STM32F43xxx devices.
12.2 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of up to 23 edge detectors for generating
event/interrupt requests. Each input line can be independently configured to select the type
(interrupt or event) and the corresponding trigger event (rising or falling or both). Each line
can also masked independently. A pending register maintains the status line of the interrupt
requests.
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