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STMicroelectronics STM32F405 User Manual
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USB on-the-go high-speed (OTG_HS)
RM0090
1480/1731
DocID018909 Rev 1
1
Figure 416. Normal bulk/control OUT/SETUP and bulk
/control IN transactio
ns - DMA
mode
1479
1481
Table of Contents
Default Chapter
2
Table of Contents
2
Documentation Conventions
57
List of Abbreviations for Registers
57
Glossary
58
Peripheral Availability
58
Memory and Bus Architecture
59
System Architecture
59
Figure 1. System Architecture for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx Devices
60
D-Bus
62
Figure 2. System Architecture for Stm32F42Xxx and Stm32F43Xxx Devices
62
I-Bus
62
S-Bus
62
Busmatrix
63
DMA Memory Bus
63
DMA Peripheral Bus
63
DMA2D Bus
63
Ethernet DMA Bus
63
LCD-TFT Controller DMA Bus
63
USB OTG HS DMA Bus
63
AHB/APB Bridges (APB)
64
Memory Organization
64
Memory Map
64
Table 1
64
Table 1. Stm32F4Xx Register Boundary Addresses
64
Bit Banding
68
Embedded SRAM
68
Flash Memory Overview
68
Boot Configuration
69
Table 2. Boot Modes
69
Table 3. Memory Mapping Vs. Boot Mode/Physical Remap in Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
71
Table 4. Memory Mapping Vs. Boot Mode/Physical Remap in Stm32F42Xxx and Stm32F43Xxx
71
Embedded Flash Memory Interface
73
Introduction
73
Main Features
73
Figure 3. Flash Memory Interface Connection Inside System Architecture (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
73
Embedded Flash Memory in Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
74
Figure 4. Flash Memory Interface Connection Inside System Architecture (Stm32F42Xxx and Stm32F43Xxx)
74
Table 5. Flash Module Organization (Stm32F40X and Stm32F41X)
75
Embedded Flash Memory in Stm32F42Xxx and Stm32F43Xxx
76
Table 6. Flash Module - 2 Mbyte Dual Bank Organization (Stm32F42Xxx and Stm32F43Xxx)
77
Mbyte Flash Memory Single Bank Vs Dual Bank Organization (Stm32F42Xxx and Stm32F43Xxx)
78
Mbyte Single Bank Flash Memory Organization (Stm32F42Xxx and Stm32F43Xxx)
78
Table 9. 1 Mbyte Dual Bank Flash Memory Organization (Stm32F42Xxx and Stm32F43Xxx)
79
Read Interface
80
Relation between CPU Clock Frequency and Flash Memory Read Time
80
Table 10. Number of Wait States According to CPU Clock (HCLK) Frequency (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
80
Table 11. Number of Wait States According to CPU Clock (HCLK) Frequency (Stm32F42Xxx and Stm32F43Xxx)
81
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
82
Figure 5. Sequential 32-Bit Instruction Execution
83
Erase and Program Operations
84
Unlocking the Flash Control Register
84
Program/Erase Parallelism
85
Erase
85
Table 12. Program/Erase Parallelism
85
Programming
86
Read-While-Write (RWW)
87
Interrupts
88
Option Bytes
88
Description of User Option Bytes
88
Table 13. Flash Interrupt Request
88
Table 14. Option Byte Organization
88
Table 15. Description of the Option Bytes (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
89
Table 16. Description of the Option Bytes (Stm32F42Xxx and Stm32F43Xxx)
90
Programming User Option Bytes
92
Read Protection (RDP)
93
Write Protections
94
Table 17. Access Versus Read Protection Level
94
Figure 6. RDP Levels
94
Proprietary Code Readout Protection (PCROP)
95
Figure 7. PCROP Levels
96
One-Time Programmable Bytes
97
Table 18. OTP Area Organization
97
Flash Interface Registers
98
Flash Access Control Register (FLASH_ACR)
98
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
98
Flash Access Control Register (FLASH_ACR)
99
For Stm32F42Xxx and Stm32F43Xxx
99
Flash Key Register (FLASH_KEYR)
100
Flash Option Key Register (FLASH_OPTKEYR)
100
Flash Status Register (FLASH_SR) for
101
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
101
Stm32F42Xxx and Stm32F43Xxx
102
Flash Control Register (FLASH_CR) for
103
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
103
Flash Control Register (FLASH_CR) for
105
Stm32F42Xxx and Stm32F43Xxx
105
Flash Option Control Register (FLASH_OPTCR) for
106
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
106
Flash Option Control Register (FLASH_OPTCR)
108
For Stm32F42Xxx and Stm32F43Xxx
108
Flash Option Control Register (FLASH_OPTCR1)
110
For Stm32F42Xxx and Stm32F43Xxx
110
Flash Interface Register Map
111
Table 19. Flash Register Map and Reset Values (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
111
Table 20. Flash Register Map and Reset Values (Stm32F42Xxx and Stm32F43Xxx)
111
CRC Calculation Unit
113
CRC Introduction
113
CRC Main Features
113
Figure 8. CRC Calculation Unit Block Diagram
113
CRC Functional Description
114
CRC Registers
114
Data Register (CRC_DR)
114
Independent Data Register (CRC_IDR)
114
Control Register (CRC_CR)
115
CRC Register Map
115
Table 21. CRC Calculation Unit Register Map and Reset Values
115
Power Controller (PWR)
116
Power Supplies
116
Figure 9. Power Supply Overview for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
116
Figure 10. Power Supply Overview for Stm32F42Xxx and Stm32F43Xxx
117
Independent A/D Converter Supply and Reference Voltage
117
Battery Backup Domain
118
Figure 11. Backup Domain
120
Voltage Regulator for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
120
Voltage Regulator for Stm32F42Xxx and Stm32F43Xxx
121
Table 22. Voltage Regulator Configuration Mode Versus Device Operating Mode
122
Power Supply Supervisor
124
Power-On Reset (Por)/Power-Down Reset (PDR)
124
Figure 12. Power-On Reset/Power-Down Reset Waveform
124
Brownout Reset (BOR)
125
Programmable Voltage Detector (PVD)
125
Figure 13. BOR Thresholds
125
Low-Power Modes
126
Figure 14. PVD Thresholds
126
Peripheral Clock Gating
128
Slowing down System Clocks
128
Table 23. Low-Power Mode Summary
128
Sleep Mode
129
Table 24. Sleep-Now Entry and Exit
129
Stop Mode (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
130
Table 25. Sleep-On-Exit Entry and Exit
130
Table 26. Stop Operating Modes (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
131
Table 27. Stop Mode Entry and Exit (for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
132
Stop Mode (Stm32F42Xxx and Stm32F43Xxx)
133
Table 28. Stop Operating Modes (Stm32F42Xxx and Stm32F43Xxx)
134
Standby Mode
136
Table 29. Stop Mode Entry and Exit (Stm32F42Xxx and Stm32F43Xxx)
136
Table 30. Standby Mode Entry and Exit
137
Programming the RTC Alternate Functions to Wake up the Device from the Stop and Standby Modes
138
Power Control Registers (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
141
PWR Power Control Register (PWR_CR)
141
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
141
PWR Power Control/Status Register (PWR_CSR)
142
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
142
Power Control Registers (Stm32F42Xxx and Stm32F43Xxx)
144
PWR Power Control Register (PWR_CR)
144
For Stm32F42Xxx and Stm32F43Xxx
144
PWR Power Control/Status Register (PWR_CSR)
147
For Stm32F42Xxx and Stm32F43Xxx
147
PWR Register Map
149
Table 31. PWR - Register Map and Reset Values for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
149
Table 32. PWR - Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx
149
Reset and Clock Control for Stm32F42Xxx and Stm32F43Xxx (RCC)
150
Reset
150
System Reset
150
Power Reset
150
Backup Domain Reset
151
Clocks
151
Figure 15. Simplified Diagram of the Reset Circuit
151
Figure 16. Clock Tree
152
Figure 17. HSE/ LSE Clock Sources
154
HSE Clock
154
HSI Clock
155
PLL Configuration
155
LSE Clock
156
LSI Clock
156
System Clock (SYSCLK) Selection
156
Clock Security System (CSS)
157
RTC/AWU Clock
157
Clock-Out Capability
158
Internal/External Clock Measurement Using TIM5/TIM11
158
Watchdog Clock
158
Figure 18. Frequency Measurement with TIM5 in Input Capture Mode
159
Figure 19. Frequency Measurement with TIM11 in Input Capture Mode
160
RCC Registers
161
RCC Clock Control Register (RCC_CR)
161
RCC PLL Configuration Register (RCC_PLLCFGR)
163
RCC Clock Configuration Register (RCC_CFGR)
165
RCC Clock Interrupt Register (RCC_CIR)
167
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
170
RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)
173
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)
174
RCC APB1 Peripheral Reset Register (RCC_APB1RSTR)
174
RCC APB2 Peripheral Reset Register (RCC_APB2RSTR)
178
RCC AHB1 Peripheral Clock Register (RCC_AHB1ENR)
180
RCC AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)
182
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)
183
RCC APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
183
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
187
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB1LPENR)
189
RCC AHB2 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB2LPENR)
192
RCC AHB3 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB3LPENR)
193
RCC APB1 Peripheral Clock Enable in Low Power Mode Register (RCC_APB1LPENR)
193
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register (RCC_APB2LPENR)
197
RCC Backup Domain Control Register (RCC_BDCR)
199
RCC Clock Control & Status Register (RCC_CSR)
200
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)
202
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)
203
RCC PLL Configuration Register (RCC_PLLSAICFGR)
206
RCC Dedicated Clock Configuration Register (RCC_DCKCFGR)
207
RCC Register Map
210
Table 33. RCC Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx
210
Reset and Clock Control for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC)
213
Reset
213
System Reset
213
Power Reset
214
Backup Domain Reset
214
Figure 20. Simplified Diagram of the Reset Circuit
214
Clocks
215
Figure 21. Clock Tree
216
HSE Clock
217
Figure 22. HSE/ LSE Clock Sources
218
HSI Clock
218
LSE Clock
219
PLL Configuration
219
Clock Security System (CSS)
220
LSI Clock
220
System Clock (SYSCLK) Selection
220
RTC/AWU Clock
221
Watchdog Clock
221
Clock-Out Capability
222
Internal/External Clock Measurement Using TIM5/TIM11
222
Figure 23. Frequency Measurement with TIM5 in Input Capture Mode
223
Figure 24. Frequency Measurement with TIM11 in Input Capture Mode
223
RCC Registers
224
RCC Clock Control Register (RCC_CR)
224
RCC PLL Configuration Register (RCC_PLLCFGR)
226
RCC Clock Configuration Register (RCC_CFGR)
228
RCC Clock Interrupt Register (RCC_CIR)
230
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
233
RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)
236
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)
237
RCC APB1 Peripheral Reset Register (RCC_APB1RSTR)
237
RCC APB2 Peripheral Reset Register (RCC_APB2RSTR)
240
RCC AHB1 Peripheral Clock Enable Register (RCC_AHB1ENR)
242
RCC AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)
244
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)
245
RCC APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
245
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
248
RCC APB2 Peripheral Clock Enable Register(RCC_APB2ENR)
250
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB1LPENR)
252
RCC AHB2 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB2LPENR)
254
RCC AHB3 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB3LPENR)
255
RCC APB1 Peripheral Clock Enable in Low Power Mode Register (RCC_APB1LPENR)
256
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register (RCC_APB2LPENR)
259
RCC Backup Domain Control Register (RCC_BDCR)
261
RCC Clock Control & Status Register (RCC_CSR)
262
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)
264
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)
265
RCC Register Map
267
Table 34. RCC Register Map and Reset Values
267
General-Purpose I/Os (GPIO)
269
GPIO Introduction
269
GPIO Main Features
269
GPIO Functional Description
269
Figure 25. Basic Structure of a Five-Volt Tolerant I/O Port Bit
270
Table 35. Port Bit Configuration Table
270
General-Purpose I/O (GPIO)
271
I/O Pin Multiplexer and Mapping
272
Table 36. Flexible SWJ-DP Pin Assignment
273
Figure 26. Selecting an Alternate Function on Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
274
Figure 27. Selecting an Alternate Function on Stm32F42Xxx and Stm32F43Xxx
275
GPIO Locking Mechanism
276
I/O Data Bitwise Handling
276
I/O Port Control Registers
276
I/O Port Data Registers
276
External Interrupt/Wakeup Lines
277
I/O Alternate Function Input/Output
277
Input Configuration
277
Figure 28. Input Floating/Pull Up/Pull down Configurations
278
Output Configuration
278
Alternate Function Configuration
279
Figure 29. Output Configuration
279
Figure 30. Alternate Function Configuration
279
Analog Configuration
280
Figure 31. High Impedance-Analog Configuration
280
Using the OSC32_IN/OSC32_OUT Pins as GPIO PC14/PC15
280
Port Pins
280
Using the OSC_IN/OSC_OUT Pins as GPIO PH0/PH1 Port Pins
280
Selection of RTC_AF1 and RTC_AF2 Alternate Functions
281
Table 38. RTC_AF2 Pin
282
GPIO Registers
283
GPIO Port Mode Register (Gpiox_Moder) (X = A..I/J/K
283
GPIO Port Output Type Register (Gpiox_Otyper)
283
(X = a
283
(X = a
284
GPIO Port Input Data Register (Gpiox_Idr) (X = a
285
GPIO Port Output Data Register (Gpiox_Odr) (X = a
285
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr) (X = a
286
(X = a
286
GPIO Alternate Function Low Register (Gpiox_Afrl) (X = a
287
(X = a
288
GPIO Register Map
288
Table 39. GPIO Register Map and Reset Values
288
System Configuration Controller (SYSCFG)
291
I/O Compensation Cell
291
SYSCFG Registers for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
291
SYSCFG Memory Remap Register (SYSCFG_MEMRMP)
291
SYSCFG Peripheral Mode Configuration Register (SYSCFG_PMC)
292
SYSCFG External Interrupt Configuration Register 1
293
(Syscfg_Exticr1)
293
(Syscfg_Exticr2)
293
SYSCFG External Interrupt Configuration Register 3
294
(Syscfg_Exticr3)
294
Compensation Cell Control Register (SYSCFG_CMPCR)
295
Table 40. SYSCFG Register Map and Reset Values (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
296
SYSCFG Peripheral Mode Configuration Register (SYSCFG_PMC)
298
SYSCFG External Interrupt Configuration Register
299
SYSCFG External Interrupt Configuration Register
300
Compensation Cell Control Register (SYSCFG_CMPCR)
302
Table 41. SYSCFG Register Map and Reset Values (Stm32F42Xxx and Stm32F43Xxx)
303
SYSCFG Register Maps for Stm32F42Xxx and Stm32F43Xxx
303
DMA Introduction
304
Figure 32. DMA Block Diagram
306
DMA Functional Description
306
Figure 33. System Implementation of the Two DMA Controllers (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx )
307
DMA Transactions
308
Figure 34. System Implementation of the Two DMA Controllers (Stm32F42Xxx and Stm32F43Xxx)
308
Figure 35. Channel Selection
309
Table 42. DMA1 Request Mapping
309
Arbiter
310
Table 43. DMA2 Request Mapping
310
DMA Streams
311
Table 44. Source and Destination Address
311
Figure 36. Peripheral-To-Memory Mode
312
Figure 37. Memory-To-Peripheral Mode
313
Figure 38. Memory-To-Memory Mode
314
Pointer Incrementation
314
Circular Mode
315
Programmable Data Width, Packing/Unpacking, Endianess
316
Table 45. Source and Destination Address Registers in Double Buffer Mode (DBM=1)
316
Table 46. Packing/Unpacking & Endian Behavior (Bit PINC = MINC = 1)
317
Single and Burst Transfers
318
Table 47. Restriction on NDT Versus PSIZE and MSIZE
318
Figure 39. FIFO Structure
319
Table 48. FIFO Threshold Configurations
320
DMA Transfer Completion
321
DMA Transfer Suspension
322
Flow Controller
323
Summary of the Possible DMA Configurations
324
Table 49. Possible DMA Configurations
324
Error Management
325
DMA Interrupts
326
Table 50. DMA Interrupt Requests
326
DMA Registers
327
DMA High Interrupt Status Register (DMA_HISR)
328
DMA Low Interrupt Flag Clear Register (DMA_LIFCR)
329
DMA Stream X Configuration Register (Dma_Sxcr) (X = 0..7)
330
DMA Stream X Number of Data Register (Dma_Sxndtr) (X = 0..7)
333
DMA Stream X Peripheral Address Register (Dma_Sxpar) (X = 0..7)
334
DMA Stream X FIFO Control Register (Dma_Sxfcr) (X = 0..7)
335
Table 51. DMA Register Map and Reset Values
337
DMA2D Introduction
341
DMA2D Main Features
342
DMA2D Control
343
Table 52. Supported Color Mode in Input
344
DMA2D Foreground and Background Pixel Format Converter (PFC)
344
Table 53. Data Order in Memory
345
DMA2D Foreground and Background CLUT Interface
346
Table 56. CLUT Data Order in Memory
347
DMA2D Blender
347
Table 57. Supported Color Mode in Output
348
Table 58. Data Order in Memory
348
DMA2D Output FIFO
348
DMA2D Transactions
349
DMA2D Transfer Control (Start, Suspend, Abort and Completion)
352
Table 59. DMA2D Interrupt Requests
353
Watermark
353
DMA2D Registers
354
DMA2D Interrupt Status Register (DMA2D_ISR)
356
DMA2D Interrupt Flag Clear Register (DMA2D_IFCR)
357
DMA2D Foreground Memory Address Register (DMA2D_FGMAR)
358
DMA2D Background Memory Address Register (DMA2D_BGMAR)
359
DMA2D Foreground Color Register (DMA2D_FGCOLR)
362
DMA2D Background PFC Control Register (DMA2D_BGPFCCR)
363
DMA2D Background Color Register (DMA2D_BGCOLR)
365
DMA2D Output PFC Control Register (DMA2D_OPFCCR)
366
DMA2D Output Color Register (DMA2D_OCOLR)
367
DMA2D Output Memory Address Register (DMA2D_OMAR)
368
DMA2D Output Offset Register (DMA2D_OOR)
369
DMA2D Line Watermark Register (DMA2D_LWR)
370
Table 60. DMA2D Register Map and Reset Values
371
Nested Vectored Interrupt Controller (NVIC)
373
Table 61. Vector Table for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
374
Table 62. Vector Table for Stm32F42Xxx and Stm32F43Xxx
377
EXTI Main Features
381
EXTI Block Diagram
382
Figure 41. External Interrupt/Event Controller Block Diagram
382
Figure 42. External Interrupt/Event GPIO Mapping (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
384
Figure 43. External Interrupt/Event GPIO Mapping (Stm32F42Xxx and Stm32F43Xxx)
385
Interrupt Mask Register (EXTI_IMR)
386
Rising Trigger Selection Register (EXTI_RTSR)
387
Software Interrupt Event Register (EXTI_SWIER)
388
EXTI Register Map
389
Table 63. External Interrupt/Event Controller Register Map and Reset Values
389
Table 64. External Interrupt/Event Controller Register Map and Reset Values
389
ADC Introduction
390
ADC Functional Description
391
Figure 44. Single ADC Block Diagram
392
ADC On-Off Control
393
Table 65. ADC Pins
393
Single Conversion Mode
394
Continuous Conversion Mode
395
Figure 45. Timing Diagram
395
Figure 46. Analog Watchdog's Guarded Area
396
Scan Mode
396
Table 66. Analog Watchdog Channel Selection
396
Figure 47. Injected Conversion Latency
397
Injected Channel Management
397
Discontinuous Mode
398
Figure 48. Right Alignment of 12-Bit Data
399
Figure 49. Left Alignment of 12-Bit Data
399
Figure 50. Left Alignment of 6-Bit Data
399
Table 67. Configuring the Trigger Polarity
400
Channel-Wise Programmable Sampling Time
400
Table 68. External Trigger for Regular Channels
401
Table 69. External Trigger for Injected Channels
402
Fast Conversion Mode
402
Data Management
403
Conversions Without DMA and Without Overrun Detection
404
Figure 51. Multi ADC Block Diagram (1)
405
Injected Simultaneous Mode
407
Figure 52. Injected Simultaneous Mode on 4 Channels: Dual ADC Mode
408
Figure 53. Injected Simultaneous Mode on 4 Channels: Triple ADC Mode
408
Regular Simultaneous Mode
408
Figure 54. Regular Simultaneous Mode on 16 Channels: Dual ADC Mode
409
Figure 55. Regular Simultaneous Mode on 16 Channels: Triple ADC Mode
409
Figure 56. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Dual ADC Mode
410
Figure 57. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Triple ADC Mode
411
Alternate Trigger Mode
411
Figure 58. Alternate Trigger: Injected Group of each ADC
412
Figure 59. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Mode
413
Figure 60. Alternate Trigger: Injected Group of each ADC
413
Combined Regular/Injected Simultaneous Mode
413
Figure 61. Alternate + Regular Simultaneous
414
Combined Regular Simultaneous + Alternate Trigger Mode
414
Figure 62. Case of Trigger Occurring During Injected Conversion
415
Temperature Sensor
415
Figure 63. Temperature Sensor and VREFINT Channel Block Diagram
416
Table 70. ADC Interrupts
417
Battery Charge Monitoring
417
ADC Registers
418
ADC Control Register 1 (ADC_CR1)
419
ADC Control Register 2 (ADC_CR2)
421
ADC Sample Time Register 1 (ADC_SMPR1)
423
ADC Injected Channel Data Offset Register X (Adc_Jofrx) (X=1..4)
424
ADC Watchdog Lower Threshold Register (ADC_LTR)
425
ADC Regular Sequence Register 2 (ADC_SQR2)
426
ADC Injected Sequence Register (ADC_JSQR)
427
ADC Regular Data Register (ADC_DR)
428
ADC Common Control Register (ADC_CCR)
429
Table 71. ADC Global Register Map
432
Table 72. ADC Register Map and Reset Values for each ADC
432
Table 73. ADC Register Map and Reset Values (Common ADC Registers)
434
Digital-To-Analog Converter (DAC)
435
Table 74. DAC Pins
436
Figure 64. DAC Channel Block Diagram
436
DAC Functional Description
437
DAC Conversion
438
Figure 65. Data Registers in Single DAC Channel Mode
438
Figure 66. Data Registers in Dual DAC Channel Mode
438
DAC Output Voltage
439
Figure 67. Timing Diagram for Conversion with Trigger Disabled TEN = 0
439
Table 75. External Triggers
439
DMA Request
440
Figure 68. DAC LFSR Register Calculation Algorithm
441
Figure 69. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
441
Triangle-Wave Generation
441
Figure 70. DAC Triangle Wave Generation
442
Figure 71. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
442
Dual DAC Channel Conversion
442
Independent Trigger with Single LFSR Generation
443
Independent Trigger with Single Triangle Generation
444
Simultaneous Trigger Without Wave Generation
445
Simultaneous Trigger with Single Triangle Generation
446
DAC Registers
447
DAC Software Trigger Register (DAC_SWTRIGR)
450
DAC Channel1 Data Output Register (DAC_DOR1)
454
Table 76. DAC Register Map
455
DAC Status Register (DAC_SR)
455
Table 77. DCMI Pins
457
Digital Camera Interface (DCMI)
457
Figure 72. DCMI Block Diagram
458
Figure 73. Top-Level Block Diagram
458
DCMI Functional Overview
458
DMA Interface
459
Figure 74. DCMI Signal Waveforms
459
Table 78. DCMI Signals
459
Table 79. Positioning of Captured Data Bytes in 32-Bit Words (8-Bit Width)
460
Table 80. Positioning of Captured Data Bytes in 32-Bit Words (10-Bit Width)
460
Table 81. Positioning of Captured Data Bytes in 32-Bit Words (12-Bit Width)
460
Figure 75. Timing Diagram
461
Synchronization
461
Table 82. Positioning of Captured Data Bytes in 32-Bit Words (14-Bit Width)
461
Capture Modes
463
Figure 76. Frame Capture Waveforms in Snapshot Mode
463
Crop Feature
464
Figure 77. Frame Capture Waveforms in Continuous Grab Mode
464
Figure 78. Coordinates and Size of the Window after Cropping
464
Figure 79. Data Capture Waveforms
465
JPEG Format
465
Figure 80. Pixel Raster Scan Order
466
Table 83. Data Storage in Monochrome Progressive Video Format
466
Data Format Description
466
Table 84. Data Storage in RGB Progressive Video Format
467
Table 85. Data Storage in Ycbcr Progressive Video Format
467
Table 86. DCMI Interrupts
467
DCMI Register Description
468
DCMI Status Register (DCMI_SR)
470
DCMI Raw Interrupt Status Register (DCMI_RIS)
471
DCMI Interrupt Enable Register (DCMI_IER)
472
DCMI Masked Interrupt Status Register (DCMI_MIS)
473
DCMI Interrupt Clear Register (DCMI_ICR)
474
DCMI Embedded Synchronization Code Register (DCMI_ESCR)
475
DCMI Embedded Synchronization Unmask Register (DCMI_ESUR)
476
DCMI Crop Window Start (DCMI_CWSTRT)
477
Table 87. DCMI Register Map and Reset Values
478
DCMI Data Register (DCMI_DR)
478
LCD-TFT Controller (LTDC)
480
Figure 81. LTDC Block Diagram
481
LTDC Functional Description
481
Table 88. LCD-TFT Pins and Signal Interface
482
Figure 82. LCD-TFT Synchronous Timings
483
Figure 83. Layer Window Programmable Parameters
485
Table 89. Pixel Data Mapping Versus Color Format
486
Figure 84. Blending Two Layers with Background
488
Figure 85. Interrupt Events
489
LTDC Interrupts
489
Table 90. LTDC Interrupt Requests
490
LTDC Programming Procedure
490
LTDC Registers
491
LTDC Active Width Configuration Register (LTDC_AWCR)
492
LTDC Total Width Configuration Register (LTDC_TWCR)
493
LTDC Shadow Reload Configuration Register (LTDC_SRCR)
495
LTDC Interrupt Enable Register (LTDC_IER)
496
LTDC Interrupt Status Register (LTDC_ISR)
497
LTDC Line Interrupt Position Configuration Register (LTDC_LIPCR)
498
LTDC Current Display Status Register (LTDC_CDSR)
499
LTDC Layerx Control Register (Ltdc_Lxcr) (Where X=1..2)
500
Ltdc_Lxwvpcr) (Where X=1..2)
501
Ltdc_Lxcfblnr) (Where X=1..2)
507
Table 91. LTDC Register Map and Reset Values
509
TIM1&TIM8 Introduction
512
TIM1&TIM8 Main Features
513
Figure 86. Advanced-Control Timer Block Diagram
514
TIM1&TIM8 Functional Description
515
Figure 87. Counter Timing Diagram with Prescaler Division Change from 1 to 2
516
Figure 88. Counter Timing Diagram with Prescaler Division Change from 1 to 4
516
Counter Modes
516
Figure 89. Counter Timing Diagram, Internal Clock Divided by 1
517
Figure 90. Counter Timing Diagram, Internal Clock Divided by 2
517
Figure 91. Counter Timing Diagram, Internal Clock Divided by 4
518
Figure 92. Counter Timing Diagram, Internal Clock Divided by N
518
Figure 93. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
518
Figure 94. Counter Timing Diagram, Update Event When ARPE=1
519
(Timx_Arr Preloaded)
519
Figure 95. Counter Timing Diagram, Internal Clock Divided by 1
520
Figure 96. Counter Timing Diagram, Internal Clock Divided by 2
520
Figure 97. Counter Timing Diagram, Internal Clock Divided by 4
520
Figure 98. Counter Timing Diagram, Internal Clock Divided by N
521
Figure 99. Counter Timing Diagram, Update Event When Repetition Counter
521
Is Not Used
521
Figure 100. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
522
Figure 101. Counter Timing Diagram, Internal Clock Divided by 2
523
Figure 102. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
523
Figure 103. Counter Timing Diagram, Internal Clock Divided by N
523
Figure 104. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
524
Figure 105. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
524
Repetition Counter
524
Figure 106. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
525
Figure 107. Control Circuit in Normal Mode, Internal Clock Divided by 1
526
Figure 108. TI2 External Clock Connection Example
526
Clock Selection
526
Figure 109. Control Circuit in External Clock Mode 1
527
Figure 110. External Trigger Input Block
528
Figure 111. Control Circuit in External Clock Mode 2
528
Capture/Compare Channels
528
Figure 112. Capture/Compare Channel (Example: Channel 1 Input Stage)
529
Figure 113. Capture/Compare Channel 1 Main Circuit
529
Figure 114. Output Stage of Capture/Compare Channel (Channel 1 to 3)
530
Figure 115. Output Stage of Capture/Compare Channel (Channel 4)
530
Input Capture Mode
530
Figure 116. PWM Input Mode Timing
532
Forced Output Mode
533
Figure 117. Output Compare Mode, Toggle on OC1
534
PWM Mode
534
Figure 118. Edge-Aligned PWM Waveforms (ARR=8)
535
Figure 119. Center-Aligned PWM Waveforms (ARR=8)
536
Complementary Outputs and Dead-Time Insertion
537
Figure 120. Complementary Output with Dead-Time Insertion
538
Figure 121. Dead-Time Waveforms with Delay Greater than the Negative Pulse
538
Figure 122. Dead-Time Waveforms with Delay Greater than the Positive Pulse
538
Using the Break Function
539
Figure 123. Output Behavior in Response to a Break
541
Figure 124. Clearing Timx Ocxref
542
Clearing the Ocxref Signal on an External Event
542
Figure 125. 6-Step Generation, COM Example (OSSR=1)
543
Step PWM Generation
543
Figure 126. Example of One Pulse Mode
544
Encoder Interface Mode
545
Table 92. Counting Direction Versus Encoder Signals
546
Figure 127. Example of Counter Operation in Encoder Interface Mode
547
Figure 128. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
547
Timer Input XOR Function
547
Interfacing with Hall Sensors
548
Figure 129. Example of Hall Sensor Interface
549
Figure 130. Control Circuit in Reset Mode
550
Timx and External Trigger Synchronization
550
Figure 131. Control Circuit in Gated Mode
551
Figure 132. Control Circuit in Trigger Mode
552
Figure 133. Control Circuit in External Clock Mode 2 + Trigger Mode
553
Table 93. Timx Internal Trigger Connection
560
TIM1&TIM8 Dma/Interrupt Enable Register (Timx_Dier)
560
TIM1&TIM8 Status Register (Timx_Sr)
562
TIM1&TIM8 Event Generation Register (Timx_Egr)
563
TIM1&TIM8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
565
TIM1&TIM8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
568
TIM1&TIM8 Capture/Compare Enable Register (Timx_Ccer)
569
Break Feature
572
Table 94. Output Control Bits for Complementary Ocx and Ocxn Channels with
572
TIM1&TIM8 Counter (Timx_Cnt)
573
TIM1&TIM8 Repetition Counter Register (Timx_Rcr)
574
TIM1&TIM8 Capture/Compare Register 2 (Timx_Ccr2)
575
TIM1&TIM8 Capture/Compare Register 4 (Timx_Ccr4)
576
TIM1&TIM8 DMA Control Register (Timx_Dcr)
578
TIM1&TIM8 DMA Address for Full Transfer (Timx_Dmar)
579
Table 95. TIM1&TIM8 Register Map and Reset Values
580
Timer Synchronization
553
TIM1&TIM8 Registers
554
TIM1&TIM8 Control Register 2 (Timx_Cr2)
555
TIM1&TIM8 Slave Mode Control Register (Timx_Smcr)
558
TIM2 to TIM5 Introduction
582
Figure 134. General-Purpose Timer Block Diagram
583
TIM2 to TIM5 Functional Description
583
Figure 135. Counter Timing Diagram with Prescaler Division Change from 1 to 2
584
Figure 136. Counter Timing Diagram with Prescaler Division Change from 1 to 4
585
Counter Modes
585
Figure 137. Counter Timing Diagram, Internal Clock Divided by 1
586
Figure 138. Counter Timing Diagram, Internal Clock Divided by 2
586
Figure 139. Counter Timing Diagram, Internal Clock Divided by 4
586
Figure 140. Counter Timing Diagram, Internal Clock Divided by N
587
Figure 141. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
587
Figure 142. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
588
Figure 143. Counter Timing Diagram, Internal Clock Divided by 1
589
Figure 144. Counter Timing Diagram, Internal Clock Divided by 2
589
Figure 145. Counter Timing Diagram, Internal Clock Divided by 4
589
Figure 146. Counter Timing Diagram, Internal Clock Divided by N
590
Figure 147. Counter Timing Diagram, Update Event
590
Figure 148. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
591
Figure 149. Counter Timing Diagram, Internal Clock Divided by 2
592
Figure 150. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
592
Figure 151. Counter Timing Diagram, Internal Clock Divided by N
592
Clock Selection
593
Figure 152. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
593
Figure 153. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
593
Figure 154. Control Circuit in Normal Mode, Internal Clock Divided by 1
594
Figure 155. TI2 External Clock Connection Example
594
Figure 156. Control Circuit in External Clock Mode 1
595
Figure 157. External Trigger Input Block
595
Capture/Compare Channels
596
Figure 158. Control Circuit in External Clock Mode 2
596
Figure 159. Capture/Compare Channel (Example: Channel 1 Input Stage)
597
Figure 160. Capture/Compare Channel 1 Main Circuit
597
Figure 161. Output Stage of Capture/Compare Channel (Channel 1)
598
Input Capture Mode
598
PWM Input Mode
599
Figure 162. PWM Input Mode Timing
600
Forced Output Mode
600
Output Compare Mode
601
Figure 163. Output Compare Mode, Toggle on OC1
602
PWM Mode
602
Figure 164. Edge-Aligned PWM Waveforms (ARR=8)
603
Figure 165. Center-Aligned PWM Waveforms (ARR=8)
604
Figure 166. Example of One-Pulse Mode
605
Clearing the Ocxref Signal on an External Event
606
Encoder Interface Mode
607
Figure 167. Clearing Timx Ocxref
607
Figure 168. Example of Counter Operation in Encoder Interface Mode
608
Table 96. Counting Direction Versus Encoder Signals
608
Figure 169. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
609
Timer Input XOR Function
609
Figure 170. Control Circuit in Reset Mode
610
Figure 171. Control Circuit in Gated Mode
611
Figure 172. Control Circuit in Trigger Mode
611
Figure 173. Control Circuit in External Clock Mode 2 + Trigger Mode
612
Timer Synchronization
612
Figure 174. Master/Slave Timer Example
613
Figure 175. Gating Timer 2 with OC1REF of Timer 1
614
Figure 176. Gating Timer 2 with Enable of Timer 1
615
Figure 177. Triggering Timer 2 with Update of Timer 1
615
Figure 178. Triggering Timer 2 with Enable of Timer 1
616
Debug Mode
617
Figure 179. Triggering Timer 1 and 2 with Timer 1 TI1 Input
617
TIM2 to TIM5 Registers
618
Timx Control Register 2 (Timx_Cr2)
620
Timx Slave Mode Control Register (Timx_Smcr)
621
Table 97. Timx Internal Trigger Connection
623
Timx Dma/Interrupt Enable Register (Timx_Dier)
623
Timx Status Register (Timx_Sr)
624
Timx Event Generation Register (Timx_Egr)
626
Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
627
Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
630
Timx Capture/Compare Enable Register (Timx_Ccer)
631
Table 98. Output Control Bit for Standard Ocx Channels
632
Timx Counter (Timx_Cnt)
633
Timx Capture/Compare Register 1 (Timx_Ccr1)
634
Timx Capture/Compare Register 3 (Timx_Ccr3)
635
Timx DMA Control Register (Timx_Dcr)
636
TIM2 Option Register (TIM2_OR)
637
TIM5 Option Register (TIM5_OR)
638
Table 99. TIM2 to TIM5 Register Map and Reset Values
639
Timx Register Map
639
TIM9 to TIM14 Introduction
641
Figure 180. General-Purpose Timer Block Diagram (TIM9 and TIM12)
642
TIM10/TIM11 and TIM13/TIM14 Main Features
642
Figure 181. General-Purpose Timer Block Diagram (TIM10/11/13/14)
643
TIM9 to TIM14 Functional Description
644
Counter Modes
645
Figure 182. Counter Timing Diagram with Prescaler Division Change from 1 to 2
645
Figure 183. Counter Timing Diagram with Prescaler Division Change from 1 to 4
645
Figure 184. Counter Timing Diagram, Internal Clock Divided by 1
646
Figure 185. Counter Timing Diagram, Internal Clock Divided by 2
646
Figure 186. Counter Timing Diagram, Internal Clock Divided by 4
647
Figure 187. Counter Timing Diagram, Internal Clock Divided by N
647
Preloaded)
647
Clock Selection
648
Preloaded)
648
Figure 190. Control Circuit in Normal Mode, Internal Clock Divided by 1
649
Figure 191. TI2 External Clock Connection Example
649
Capture/Compare Channels
650
Figure 192. Control Circuit in External Clock Mode 1
650
Figure 193. Capture/Compare Channel (Example: Channel 1 Input Stage)
650
Figure 194. Capture/Compare Channel 1 Main Circuit
651
Figure 195. Output Stage of Capture/Compare Channel (Channel 1)
651
Input Capture Mode
651
Figure 196. PWM Input Mode Timing
653
PWM Input Mode (Only for TIM9/12)
653
Forced Output Mode
654
Figure 197. Output Compare Mode, Toggle on OC1
655
PWM Mode
655
Figure 198. Edge-Aligned PWM Waveforms (ARR=8)
656
One-Pulse Mode
656
Figure 199. Example of One Pulse Mode
657
Figure 200. Control Circuit in Reset Mode
658
TIM9/12 External Trigger Synchronization
658
Figure 201. Control Circuit in Gated Mode
659
Figure 202. Control Circuit in Trigger Mode
660
Timer Synchronization (TIM9/12)
660
TIM9 and TIM12 Registers
661
TIM9/12 Slave Mode Control Register (Timx_Smcr)
663
Table 100. Timx Internal Trigger Connection
664
TIM9/12 Interrupt Enable Register (Timx_Dier)
664
TIM9/12 Status Register (Timx_Sr)
666
TIM9/12 Event Generation Register (Timx_Egr)
667
TIM9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)
669
TIM9/12 Capture/Compare Enable Register (Timx_Ccer)
672
Table 101. Output Control Bit for Standard Ocx Channels
673
TIM9/12 Counter (Timx_Cnt)
673
TIM9/12 Capture/Compare Register 1 (Timx_Ccr1)
674
Table 102. TIM9/12 Register Map and Reset Values
675
TIM10/11/13/14 Registers
677
TIM10/11/13/14 Interrupt Enable Register (Timx_Dier)
678
TIM10/11/13/14 Event Generation Register (Timx_Egr)
679
TIM10/11/13/14 Capture/Compare Mode Register
680
Table 103. Output Control Bit for Standard Ocx Channels
683
TIM10/11/13/14 Counter (Timx_Cnt)
684
TIM10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
685
Table 104. TIM10/11/13/14 Register Map and Reset Values
686
Basic Timers (TIM6&TIM7)
688
Figure 203. Basic Timer Block Diagram
688
TIM6&TIM7 Functional Description
689
Figure 204. Counter Timing Diagram with Prescaler Division Change from 1 to 2
690
Figure 205. Counter Timing Diagram with Prescaler Division Change from 1 to 4
690
Counting Mode
690
Figure 206. Counter Timing Diagram, Internal Clock Divided by 1
691
Figure 207. Counter Timing Diagram, Internal Clock Divided by 2
691
Figure 208. Counter Timing Diagram, Internal Clock Divided by 4
692
Figure 209. Counter Timing Diagram, Internal Clock Divided by N
692
Preloaded)
692
Preloaded)
693
Figure 212. Control Circuit in Normal Mode, Internal Clock Divided by 1
693
Clock Source
693
TIM6&TIM7 Registers
694
TIM6&TIM7 Control Register 2 (Timx_Cr2)
695
TIM6&TIM7 Status Register (Timx_Sr)
696
TIM6&TIM7 Prescaler (Timx_Psc)
697
Table 105. TIM6&TIM7 Register Map and Reset Values
698
Independent Watchdog (IWDG)
699
Table 106. Min/Max IWDG Timeout Period at 32 Khz (LSI)
700
Figure 213. Independent Watchdog Block Diagram
700
Debug Mode
700
IWDG Registers
701
Reload Register (IWDG_RLR)
702
Table 107. IWDG Register Map and Reset Values
703
Window Watchdog (WWDG)
704
Figure 214. Watchdog Block Diagram
705
Figure 215. Window Watchdog Timing Diagram
706
How to Program the Watchdog Timeout
706
Table 108. Minimum and Maximum Timeout Values at 30 Mhz
707
Pclk1 )
707
Debug Mode
707
WWDG Registers
708
Configuration Register (WWDG_CFR)
709
Table 109. WWDG Register Map and Reset Values
710
Table 110. Number of Cycles Required to Process each 128-Bit Block
711
(Stm32F415/417Xx)
711
(Stm32F43Xxx)
711
CRYP Introduction
711
Figure 216. Block Diagram (Stm32F415/417Xx)
713
CRYP Functional Description
713
DES/TDES Cryptographic Core
714
Figure 217. Block Diagram (Stm32F43Xxx)
714
Figure 218. DES/TDES-ECB Mode Encryption
716
Figure 219. DES/TDES-ECB Mode Decryption
716
Figure 220. DES/TDES-CBC Mode Encryption
718
AES Cryptographic Core
719
Figure 221. DES/TDES-CBC Mode Decryption
719
Figure 222. AES-ECB Mode Encryption
720
Figure 223. AES-ECB Mode Decryption
721
Figure 224. AES-CBC Mode Encryption
722
Figure 225. AES-CBC Mode Decryption
723
Figure 226. AES-CTR Mode Encryption
724
Figure 227. AES-CTR Mode Decryption
725
Figure 228. Initial Counter Block Structure for the Counter Mode
725
Data Type
730
Table 112. Data Types
731
Figure 229. 64-Bit Block Construction According to DATATYPE
732
Initialization Vectors - CRYP_IV0...1(L/R)
733
CRYP Busy State
734
Figure 230. Initialization Vectors Use in the TDES-CBC Encryption
734
Procedure to Perform an Encryption or a Decryption
735
Context Swapping
736
CRYP Interrupts
738
Figure 231. CRYP Interrupt Mapping Diagram
739
CRYP DMA Interface
739
CRYP Control Register (CRYP_CR) for Stm32F415/417Xx
741
CRYP Status Register (CRYP_SR)
744
CRYP Data Input Register (CRYP_DIN)
745
CRYP Data Output Register (CRYP_DOUT)
746
CRYP DMA Control Register (CRYP_DMACR)
747
CRYP Raw Interrupt Status Register (CRYP_RISR)
748
CRYP Key Registers (CRYP_K0...3(L/R)R)
749
CRYP Initialization Vector Registers (CRYP_IV0...1(L/R)R)
751
CRYP Context Swap Registers (CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R) for Stm32F42Xxx and Stm32F43Xxx
753
Table 113. CRYP Register Map and Reset Values for Stm32F415/417Xx
754
Table 114. CRYP Register Map and Reset Values for Stm32F43Xxx
755
Figure 232. Block Diagram
758
RNG Introduction
758
Operation
759
RNG Control Register (RNG_CR)
760
RNG Data Register (RNG_DR)
761
Table 115. RNG Register Map and Reset Map
762
HASH Introduction
763
Figure 233. Block Diagram for Stm32F415/417Xx
764
HASH Functional Description
764
Figure 234. Block Diagram for Stm32F43Xxx
765
Duration of the Processing
766
Figure 235. Bit, Byte and Half-Word Swapping
767
Message Digest Computing
768
Message Padding
769
Hash Operation
770
Context Swapping
771
Figure 236. HASH Interrupt Mapping Diagram
773
HASH Control Register (HASH_CR) for Stm32F43Xxx
776
HASH Data Input Register (HASH_DIN)
779
HASH Start Register (HASH_STR)
780
HASH Digest Registers (HASH_HR0..4/5/6/7)
781
HASH Interrupt Enable Register (HASH_IMR)
783
HASH Status Register (HASH_SR)
784
HASH Context Swap Registers (Hash_Csrx)
785
Table 116. HASH Register Map and Reset Values on Stm32F415/417Xx
786
Table 117. HASH Register Map and Reset Values on Stm32F43Xxx
787
Introduction
789
RTC Main Features
790
Figure 237. RTC Block Diagram
791
RTC Functional Description
791
Real-Time Clock and Calendar
792
Periodic Auto-Wakeup
793
RTC Initialization and Configuration
794
Reading the Calendar
795
Resetting the RTC
796
RTC Reference Clock Detection
797
RTC Coarse Digital Calibration
798
RTC Smooth Digital Calibration
799
Timestamp Function
801
Tamper Detection
802
Calibration Clock Output
803
Table 118. Effect of Low-Power Modes on RTC
804
Alarm Output
804
Table 119. Interrupt Control Bits
805
RTC Interrupts
805
RTC Registers
806
RTC Date Register (RTC_DR)
807
RTC Control Register (RTC_CR)
808
RTC Initialization and Status Register (RTC_ISR)
810
RTC Prescaler Register (RTC_PRER)
813
RTC Calibration Register (RTC_CALIBR)
814
RTC Alarm a Register (RTC_ALRMAR)
815
RTC Alarm B Register (RTC_ALRMBR)
816
RTC Write Protection Register (RTC_WPR)
817
RTC Shift Control Register (RTC_SHIFTR)
818
RTC Time Stamp Date Register (RTC_TSDR)
819
RTC Timestamp Sub Second Register (RTC_TSSSR)
820
RTC Alarm a Sub Second Register (RTC_ALRMASSR)
824
RTC Alarm B Sub Second Register (RTC_ALRMBSSR)
825
Table 120. RTC Register Map and Reset Values
826
RTC Backup Registers (Rtc_Bkpxr)
826
Inter-Integrated Circuit (I 2 C) Interface
829
Mode Selection
830
Figure 238. I2C Bus Protocol
831
Figure 239. I2C Block Diagram for Stm32F40X/41X
832
Figure 240. I2C Block Diagram for Stm32F42X/43X
833
Figure 241. Transfer Sequence Diagram for Slave Transmitter
835
Figure 242. Transfer Sequence Diagram for Slave Receiver
836
Figure 243. Transfer Sequence Diagram for Master Transmitter
839
Figure 244. Transfer Sequence Diagram for Master Receiver
841
Error Conditions
842
Table 121. Maximum DNF[3:0] Value to be Compliant with Thd:dat(Max)
843
Programmable Noise Filter
843
SDA/SCL Line Control
844
Table 122. Smbus Vs. I2C
845
DMA Requests
847
Packet Error Checking
848
Table 123. I2C Interrupt Requests
849
Figure 245. I2C Interrupt Mapping Diagram
850
Table 124. I2C Register Map and Reset Values
864
SPI Introduction
865
SPI Features
866
Figure 246. SPI Block Diagram
868
SPI Functional Description
868
Figure 247. Single Master/ Single Slave Application
869
Configuring the SPI in Slave Mode
871
Figure 248. Data Clock Timing Diagram
871
Figure 249. TI Mode - Slave Mode, Single Transfer
873
Figure 250. TI Mode - Slave Mode, Continuous Transfer
873
Configuring the SPI in Master Mode
874
Figure 251. TI Mode - Master Mode, Single Transfer
875
Figure 252. TI Mode - Master Mode, Continuous Transfer
875
Configuring the SPI for Half-Duplex Communication
876
Figure 253. TXE/RXNE/BSY Behavior in Master / Full-Duplex Mode (BIDIMODE=0 and RXONLY=0) in the Case of Continuous Transfers
879
Figure 254. TXE/RXNE/BSY Behavior in Slave / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the Case of Continuous Transfers
879
Case of Continuous Transfers
880
Figure 255. TXE/BSY Behavior in Master Transmit-Only Mode (BIDIMODE=0 and RXONLY=0) in
880
Continuous Transfers
881
Figure 256. TXE/BSY in Slave Transmit-Only Mode (BIDIMODE=0 and RXONLY=0) in the Case of
881
Figure 257. RXNE Behavior in Receive-Only Mode (BIDIRMODE=0 and RXONLY=1)
882
In the Case of Continuous Transfers
882
CRC Calculation
883
Figure 258. TXE/BSY Behavior When Transmitting (BIDIRMODE=0 and RXONLY=0)
883
In the Case of Discontinuous Transfers
883
Status Flags
885
Disabling the SPI
886
SPI Communication Using DMA (Direct Memory Addressing)
887
Figure 259. Transmission Using DMA
888
Figure 260. Reception Using DMA
888
Error Flags
889
Figure 261. TI Mode Frame Format Error Detection
890
SPI Interrupts
890
Table 125. SPI Interrupt Requests
890
Figure 262. I 2 S Block Diagram
891
Figure 263. I2S Full Duplex Block Diagram
892
Supported Audio Protocols
893
Figure 264. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, CPOL = 0)
894
Figure 265. I 2 S Philips Standard Waveforms (24-Bit Frame with CPOL = 0)
894
Figure 266. Transmitting 0X8Eaa33
895
Figure 267. Receiving 0X8Eaa33
895
Figure 268. I
895
Figure 269. Example
896
Figure 270. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length with CPOL = 0
896
Figure 271. MSB Justified 24-Bit Frame Length with CPOL = 0
897
Figure 272. MSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
897
Figure 273. LSB Justified 16-Bit or 32-Bit Full-Accuracy with CPOL = 0
897
Figure 274. LSB Justified 24-Bit Frame Length with CPOL = 0
898
Figure 275. Operations Required to Transmit 0X3478Ae
898
Figure 276. Operations Required to Receive 0X3478Ae
898
Figure 277. LSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
899
Figure 278. Example of LSB Justified 16-Bit Extended to 32-Bit Packet Frame
899
Figure 279. PCM Standard Waveforms (16-Bit)
900
Figure 280. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)
900
Clock Generator
901
Figure 281. Audio Sampling Frequency Definition
901
Figure 282. I
901
Table 126. Audio Frequency Precision (for PLLM VCO = 1 Mhz or 2 Mhz)
902
Status Flags
906
Error Flags
907
DMA Features
908
Table 127. I
908
SPI Control Register 2 (SPI_CR2)
911
SPI Status Register (SPI_SR)
912
SPI Data Register (SPI_DR)
913
Table 128. SPI Register Map and Reset Values
918
Serial Audio Interface (SAI)
919
Main Features
920
Figure 283. Functional Block Diagram
921
Main SAI Modes
922
Figure 284. Audio Frame
923
SAI Synchronization Mode
923
Frame Length
924
Frame Synchronization Active Level Length
925
Figure 285. FS Role Is Start of Frame + Channel Side Identification (FSDEF = TRIS = 1)
926
Figure 286. FS Role Is Start of Frame (FSDEF = 0)
926
Slot Configuration
926
Figure 287. Slot Size Configuration with FBOFF = 0 in Sai_Xslotr
927
Figure 288. First Bit Offset
927
Figure 289. Audio Block Clock Generator Overview
928
SAI Clock Generator
928
Table 129. Example of Possible Audio Frequency Sampling Range
929
Internal Fifos
929
Figure 290. AC'97 Audio Frame
932
AC'97 Link Controller
932
Specific Features
933
Companding Mode
934
Figure 291. Data Companding Hardware in an Audio Block in the SAI
934
Output Data Line Management on an Inactive Slot
935
Figure 292. Tristate Strategy on SD Output Line on an Inactive Slot
936
Error Flags
937
Figure 293. Tristate on Output Data Line in a Protocol Like I2S
937
Figure 294. Overrun Detection Error
938
Anticipated Frame Synchronisation Detection (AFSDET)
939
Figure 295. FIFO Underrun Event
939
Codec Not Ready (CNRDY AC'97)
940
Table 130. Interrupt Sources
941
SAI DMA Interface
942
SAI Registers
943
SAI Xconfiguration Register 2 (Sai_Xcr2) Where X Is a or B
946
SAI Xframe Configuration Register (SAI_XFRCR) Where X Is a or B
948
SAI Xslot Register (Sai_Xslotr) Where X Is a or B
950
SAI Xinterrupt Mask Register2(Sai_Xim) Where X Is a or B
951
SAI Xstatus Register (Sai_Xsr) Where X Is a or B
953
SAI Xclear Flag Register (Sai_Xclrfr) Where X Is a or B
955
Table 131. SAI Register Map and Reset Values
956
SAI Xdata Register (Sai_Xdr) Where X Is a or B
956
Transmitter (USART)
958
USART Functional Description
959
Figure 296. USART Block Diagram
961
Figure 297. Word Length Programming
962
USART Character Description
962
Transmitter
963
Figure 298. Configurable Stop Bits
964
Figure 299. TC/TXE Behavior When Transmitting
965
Figure 300. Start Bit Detection When Oversampling by 16 or 8
966
Receiver
966
Figure 301. Data Sampling When Oversampling by 16
969
Figure 302. Data Sampling When Oversampling by 8
970
Table 132. Noise Detection from Sampled Data
970
Fractional Baud Rate Generation
971
Oversampling by 16
973
Table 133. Error Calculation for Programmed Baud Rates at F
973
PCLK = 8 Mhz or F PCLK = 12 Mhz
973
Oversampling by 8
974
Oversampling by 16
974
PCLK = 16 Mhz or F PCLK = 24 Mhz
974
Oversampling by 8
975
Oversampling by 16
976
Oversampling by 8
976
Oversampling by 16
977
Oversampling by 8
978
Oversampling by 16
979
Oversampling by 8
980
USART Receiver Tolerance to Clock Deviation
981
Table 143. USART Receiver's Tolerance When DIV Fraction Is 0
982
Table 144. USART Receiver Tolerance When Div_Fraction Is Different from 0
982
Multiprocessor Communication
982
Figure 303. Mute Mode Using Idle Line Detection
983
Table 145. Frame Formats
984
Figure 304. Mute Mode Using Address Mark Detection
984
Parity Control
984
LIN (Local Interconnection Network) Mode
985
Figure 305. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
986
Figure 306. Break Detection in LIN Mode Vs. Framing Error Detection
987
USART Synchronous Mode
987
Figure 307. USART Example of Synchronous Transmission
988
Figure 308. USART Data Clock Timing Diagram (M=0)
988
Figure 309. USART Data Clock Timing Diagram (M=1)
989
Figure 310. RX Data Setup/Hold Time
989
Single-Wire Half-Duplex Communication
989
Figure 311. ISO 7816-3 Asynchronous Protocol
990
Smartcard
990
Figure 312. Parity Error Detection Using the 1.5 Stop Bits
991
Irda SIR ENDEC Block
992
Figure 313. Irda SIR ENDEC- Block Diagram
993
Figure 314. Irda Data Modulation (3/16) -Normal Mode
993
Continuous Communication Using DMA
994
Figure 315. Transmission Using DMA
995
Figure 316. Reception Using DMA
996
Figure 317. Hardware Flow Control between 2 Usarts
996
Figure 318. RTS Flow Control
997
Figure 319. CTS Flow Control
997
Table 146. USART Interrupt Requests
998
Figure 320. USART Interrupt Mapping Diagram
998
USART Interrupts
998
Table 147. USART Mode Configuration
999
Data Register (USART_DR)
1002
Control Register 2 (USART_CR2)
1005
Control Register 3 (USART_CR3)
1006
Guard Time and Prescaler Register (USART_GTPR)
1009
Table 148. USART Register Map and Reset Values
1010
SDIO Main Features
1011
Figure 321. SDIO "No Response" and "No Data" Operations
1012
Figure 322. SDIO (Multiple) Block Read Operation
1012
Figure 323. SDIO (Multiple) Block Write Operation
1013
Figure 324. SDIO Sequential Read Operation
1013
Figure 325. SDIO Sequential Write Operation
1013
Figure 326. SDIO Block Diagram
1014
SDIO Functional Description
1014
Figure 327. SDIO Adapter
1015
Table 149. SDIO I/O Definitions
1015
Figure 328. Control Unit
1016
Figure 329. SDIO Adapter Command Path
1017
Figure 330. Command Path State Machine (CPSM)
1018
Figure 331. SDIO Command Transfer
1019
Table 150. Command Format
1019
Table 151. Short Response Format
1020
Table 152. Long Response Format
1020
Table 153. Command Path Status Flags
1020
Figure 332. Data Path
1021
Figure 333. Data Path State Machine (DPSM)
1022
Table 154. Data Token Format
1023
Table 155. Transmit FIFO Status Flags
1024
SDIO APB2 Interface
1025
Table 156. Receive FIFO Status Flags
1025
Card Functional Description
1026
Card Identification Process
1027
Block Write
1028
Block Read
1029
Erase: Group Erase and Sector Erase
1031
Card Status Register
1034
Table 157. Card Status
1035
SD Status Register
1037
Table 158. SD Status
1038
Table 159. Speed Class Code Field
1039
Table 160. Performance Move Field
1039
Table 161. AU_SIZE Field
1040
Table 162. Maximum au Size
1040
Table 163. Erase Size Field
1040
Table 164. Erase Timeout Field
1041
Table 165. Erase Offset Field
1041
SD I/O Mode
1041
Commands and Responses
1042
Table 166. Block-Oriented Write Commands
1043
Table 167. Block-Oriented Write Protection Commands
1044
Table 168. Erase Commands
1044
Table 169. I/O Mode Commands
1045
Table 170. Lock Card
1045
Table 171. Application-Specific Commands
1045
Table 172. R1 Response
1046
Response Formats
1046
R3 (OCR Register)
1047
Table 173. R2 Response
1047
Table 174. R3 Response
1047
Table 175. R4 Response
1047
R5 (Interrupt Request)
1048
Table 176. R4B Response
1048
Table 177. R5 Response
1048
Table 178. R6 Response
1049
SDIO I/O Card-Specific Operations
1049
SDIO I/O Read Wait Operation by SDIO_D2 Signaling
1050
CE-ATA Specific Operations
1051
HW Flow Control
1052
SDI Clock Control Register (SDIO_CLKCR)
1053
SDIO Argument Register (SDIO_ARG)
1054
SDIO Command Register (SDIO_CMD)
1055
Table 179. Response Type and Sdio_Respx Registers
1056
SDIO Command Response Register (SDIO_RESPCMD)
1056
SDIO Data Timer Register (SDIO_DTIMER)
1057
SDIO Data Control Register (SDIO_DCTRL)
1058
SDIO Data Counter Register (SDIO_DCOUNT)
1059
SDIO Status Register (SDIO_STA)
1060
SDIO Interrupt Clear Register (SDIO_ICR)
1061
SDIO Mask Register (SDIO_MASK)
1063
SDIO FIFO Counter Register (SDIO_FIFOCNT)
1065
Table 180. SDIO Register Map
1066
SDIO Data FIFO Register (SDIO_FIFO)
1066
Bxcan Introduction
1068
Figure 334. CAN Network Topology
1069
Bxcan General Description
1069
Control, Status and Configuration Registers
1070
Figure 335. Dual CAN Block Diagram
1071
Bxcan Operating Modes
1071
Initialization Mode
1072
Figure 336. Bxcan Operating Modes
1073
Test Mode
1073
Figure 337. Bxcan in Silent Mode
1074
Figure 338. Bxcan in Loop Back Mode
1074
Figure 339. Bxcan in Combined Mode
1075
Debug Mode
1075
Figure 340. Transmit Mailbox States
1076
Figure 341. Receive FIFO States
1077
Time Triggered Communication Mode
1077
Identifier Filtering
1078
Figure 342. Filter Bank Scale Configuration - Register Organization
1080
Figure 343. Example of Filter Numbering
1081
Figure 344. Filtering Mechanism - Example
1082
Message Storage
1082
Figure 345. CAN Error State Diagram
1083
Table 181. Transmit Mailbox Mapping
1083
Table 182. Receive Mailbox Mapping
1083
Error Management
1084
Figure 346. Bit Timing
1085
Figure 347. CAN Frames
1086
Bxcan Interrupts
1086
Figure 348. Event Flags and Interrupt Generation
1087
CAN Registers
1088
CAN Mailbox Registers
1098
Figure 349. RX and TX Mailboxes
1098
CAN Filter Registers
1105
Table 183. Bxcan Register Map and Reset Values
1109
DMA Controller
1113
Ethernet Introduction
1113
MAC Core Features
1114
DMA Features
1115
Table 184. Alternate Function Mapping
1116
Ethernet Pins
1116
Figure 350. ETH Block Diagram
1117
Ethernet Functional Description: SMI, MII and RMII
1117
Figure 351. SMI Interface Signals
1118
Table 185. Management Frame Format
1118
Figure 352. MDIO Timing and Frame Structure - Write Cycle
1119
Figure 353. MDIO Timing and Frame Structure - Read Cycle
1120
Media-Independent Interface: MII
1120
Table 186. Clock Range
1120
Figure 354. Media Independent Interface Signals
1121
Table 187. TX Interface Signal Encoding
1122
Table 188. RX Interface Signal Encoding
1122
Figure 355. MII Clock Sources
1123
Figure 356. Reduced Media-Independent Interface Signals
1123
Reduced Media-Independent Interface: RMII
1123
Figure 357. RMII Clock Sources
1124
Figure 358. Clock Scheme
1124
MII/RMII Selection
1124
Ethernet Functional Description: MAC 802.3
1125
Figure 359. Address Field Format
1126
Figure 360. MAC Frame Format
1128
Figure 361. Tagged MAC Frame Format
1128
MAC Frame Transmission
1129
Figure 362. Transmission Bit Order
1135
Figure 363. Transmission with no Collision
1135
Figure 364. Transmission with Collision
1136
Figure 365. Frame Transmission in MMI and RMII Modes
1136
MAC Frame Reception
1136
Table 189. Frame Statuses
1138
Figure 366. Receive Bit Order
1140
Figure 367. Reception with no Error
1141
Figure 368. Reception with Errors
1141
Figure 369. Reception with False Carrier Indication
1141
MAC Interrupts
1141
Figure 370. MAC Core Interrupt Masking Scheme
1142
MAC Filtering
1142
Table 190. Destination Address Filtering
1144
MAC Loopback Mode
1145
Table 191. Source Address Filtering
1145
Power Management: PMT
1146
Figure 371. Wakeup Frame Filter Register
1147
Precision Time Protocol (IEEE1588 PTP)
1149
Figure 372. Networked Time Synchronization
1150
Figure 373. System Time Update Using the Fine Correction Method
1152
Figure 374. PTP Trigger Output to TIM2 ITR1 Connection
1154
Figure 375. PPS Output
1155
Ethernet Functional Description: DMA Controller Operation
1155
Figure 376. Descriptor Ring and Chain Structure
1156
Initialization of a Transfer Using DMA
1156
Host Data Buffer Alignment
1157
DMA Arbiter
1158
Figure 377. Txdma Operation in Default Mode
1160
Figure 378. Txdma Operation in OSF Mode
1162
Figure 379. Normal Transmit Descriptor
1163
Figure 380. Enhanced Transmit Descriptor
1169
Rx DMA Configuration
1170
Figure 381. Receive DMA Operation
1171
Figure 382. Normal Rx DMA Descriptor Structure
1173
Table 192. Receive Descriptor 0 - Encoding for Bits 7, 5 and 0 (Normal Descriptor Format Only, EDFE=0)
1176
Figure 383. Enhanced Receive Descriptor Field Format with IEEE1588 Time Stamp Enabled
1179
DMA Interrupts
1181
Figure 384. Interrupt Scheme
1182
Ethernet Interrupts
1182
Ethernet Register Descriptions
1183
Figure 385. Ethernet MAC Remote Wakeup Frame Filter Register (ETH_MACRWUFFR)
1192
MMC Register Description
1202
IEEE 1588 Time Stamp Registers
1207
Table 193. Time Stamp Snapshot Dependency on Registers Bits
1209
DMA Register Description
1215
Ethernet Register Maps
1229
Table 194. Ethernet Register Map and Reset Values
1229
OTG_FS Introduction
1233
General Features
1234
Figure 386. OTG Full-Speed Block Diagram
1235
Peripheral-Mode Features
1235
OTG Full-Speed Core
1236
Figure 387. OTG A-B Device Connection
1237
OTG Dual Role Device (DRD)
1237
SRP Dual Role Device
1238
Figure 388. USB Peripheral-Only Connection
1239
SRP-Capable Peripheral
1239
Peripheral Endpoints
1240
USB Host
1242
Figure 389. USB Host-Only Connection
1243
SRP-Capable Host
1243
Host Channels
1245
Host Scheduler
1246
Figure 390. SOF Connectivity
1247
SOF Trigger
1247
Peripheral Sofs
1248
Figure 391. Updating OTG_FS_HFIR Dynamically
1249
Dynamic Update of the OTG_FS_HFIR Register
1249
Figure 392. Device-Mode FIFO Address Mapping and AHB FIFO Access Mapping
1250
USB Data Fifos
1250
Figure 393. Host-Mode FIFO Address Mapping and AHB FIFO Access Mapping
1251
Peripheral Tx Fifos
1251
Host Tx Fifos
1252
Host Mode
1253
OTG_FS Interrupts
1254
Figure 394. Interrupt Hierarchy
1255
OTG_FS Control and Status Registers
1255
Figure 395. CSR Memory Map
1257
Table 195. Core Global Control and Status Registers (Csrs)
1257
Table 196. Host-Mode Control and Status Registers (Csrs)
1258
Table 197. Device-Mode Control and Status Registers
1259
Table 198. Data FIFO (DFIFO) Access Register Map
1261
Table 199. Power and Clock Gating Control and Status Registers
1261
OTG_FS Global Registers
1262
Table 200. TRDT Values
1267
Host-Mode Registers
1283
Device-Mode Registers
1293
Table 201. Minimum Duration for Soft Disconnect
1295
Table 202. OTG_FS Register Map and Reset Values
1315
OTG_FS Programming Model
1324
Host Initialization
1325
Host Programming Model
1326
Figure 396. Transmit FIFO Write Task
1327
Figure 397. Receive FIFO Read Task
1328
Figure 398. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions
1329
Figure 399. Bulk/Control in Transactions
1332
Figure 400. Normal Interrupt OUT/IN Transactions
1334
Figure 401. Normal Isochronous OUT/IN Transactions
1339
Device Programming Model
1342
Operational Model
1344
Figure 402. Receive FIFO Packet Read
1345
Figure 403. Processing a SETUP Packet
1347
Figure 404. Bulk out Transaction
1353
Worst Case Response Time
1360
Figure 405. TRDT Max Timing Case
1362
OTG Programming Model
1362
Figure 406. A-Device SRP
1363
Figure 407. B-Device SRP
1364
Figure 408. A-Device HNP
1365
Figure 409. B-Device HNP
1367
USB On-The-Go High-Speed (OTG_HS)
1369
General Features
1370
Host-Mode Features
1371
Figure 410. USB OTG Interface Block Diagram
1372
High-Speed OTG PHY
1372
OTG Dual-Role Device
1373
USB Functional Description in Peripheral Mode
1374
Peripheral Endpoints
1375
USB Functional Description on Host Mode
1378
Host Channels
1380
Host Scheduler
1381
SOF Trigger
1382
Peripheral Sofs
1383
USB_HS Power Modes
1384
FIFO RAM Allocation
1385
Figure 411. Updating OTG_HS_HFIR Dynamically
1385
OTG_HS Interrupts
1386
Figure 412. Interrupt Hierarchy
1387
OTG_HS Control and Status Registers
1387
CSR Memory Map
1388
Figure 413. CSR Memory Map
1389
Table 203. Core Global Control and Status Registers (Csrs)
1389
Table 204. Host-Mode Control and Status Registers (Csrs)
1390
Table 205. Device-Mode Control and Status Registers
1391
OTG_HS Global Registers
1393
Table 208. TRDT Values
1400
Host-Mode Registers
1418
Device-Mode Registers
1430
Table 206. Data FIFO (DFIFO) Access Register Map
1393
Table 207. Power and Clock Gating Control and Status Registers
1393
Table 209. Minimum Duration for Soft Disconnect
1433
Table 210. OTG_HS Register Map and Reset Values
1458
OTG_HS Programming Model
1473
Host Initialization
1474
Device Initialization
1475
Figure 414. Transmit FIFO Write Task
1478
Figure 415. Receive FIFO Read Task
1479
Figure 416. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions - DMA
1480
Mode
1480
Figure 417. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions - Slave
1481
Mode
1481
Figure 418. Bulk/Control in Transactions - DMA Mode
1484
Figure 419. Bulk/Control in Transactions - Slave Mode
1485
Figure 420. Normal Interrupt OUT/IN Transactions - DMA Mode
1487
Figure 421. Normal Interrupt OUT/IN Transactions - Slave Mode
1488
Figure 422. Normal Isochronous OUT/IN Transactions - DMA Mode
1493
Figure 423. Normal Isochronous OUT/IN Transactions - Slave Mode
1494
Device Programming Model
1502
Operational Model
1504
Figure 424. Receive FIFO Packet Read in Slave Mode
1505
Figure 425. Processing a SETUP Packet
1507
Figure 426. Slave Mode Bulk out Transaction
1514
Worst Case Response Time
1522
Figure 427. TRDT Max Timing Case
1523
Figure 428. A-Device SRP
1524
OTG Programming Model
1524
Figure 429. B-Device SRP
1525
Figure 430. A-Device HNP
1526
Figure 431. B-Device HNP
1528
Flexible Static Memory Controller (FSMC)
1530
Figure 432. FSMC Block Diagram
1531
Supported Memories and Transactions
1532
Table 211. NOR/PSRAM Bank Selection
1533
Figure 433. FSMC Memory Banks
1533
External Device Address Mapping
1533
NAND/PC Card Address Mapping
1534
Table 212. External Memory Address
1534
Table 213. Memory Mapping and Timing Registers
1534
Table 214. NAND Bank Selections
1535
NOR Flash/Psram Controller
1535
External Memory Interface Signals
1536
Table 215. Programmable NOR/PSRAM Access Parameters
1536
Table 216. Nonmultiplexed I/O nor Flash
1536
Table 217. Multiplexed I/O nor Flash
1537
Table 218. Nonmultiplexed I/Os PSRAM/SRAM
1537
Table 219. Multiplexed I/O PSRAM
1537
And Transactions
1538
Supported Memories and Transactions
1538
Table 220. nor Flash/Psram Controller: Example of Supported Memories
1538
General Timing Rules
1539
Figure 434. Mode1 Read Accesses
1540
NOR Flash/Psram Controller Asynchronous Transactions
1540
Figure 435. Mode1 Write Accesses
1541
Table 221. Fsmc_Bcrx Bit Fields
1541
Table 222. Fsmc_Btrx Bit Fields
1542
Figure 436. Modea Read Accesses
1543
Figure 437. Modea Write Accesses
1543
Table 223. Fsmc_Bcrx Bit Fields
1544
Table 224. Fsmc_Btrx Bit Fields
1544
Figure 438. Mode2 and Mode B Read Accesses
1545
Table 225. Fsmc_Bwtrx Bit Fields
1545
Figure 439. Mode2 Write Accesses
1546
Figure 440. Mode B Write Accesses
1546
Table 226. Fsmc_Bcrx Bit Fields
1547
Table 227. Fsmc_Btrx Bit Fields
1547
Figure 441. Mode C Read Accesses
1548
Table 228. Fsmc_Bwtrx Bit Fields
1548
Figure 442. Mode C Write Accesses
1549
Table 229. Fsmc_Bcrx Bit Fields
1549
Table 230. Fsmc_Btrx Bit Fields
1550
Table 231. Fsmc_Bwtrx Bit Fields
1550
Figure 443. Mode D Read Accesses
1551
Figure 444. Mode D Write Accesses
1551
Table 232. Fsmc_Bcrx Bit Fields
1552
Table 233. Fsmc_Btrx Bit Fields
1552
Figure 445. Multiplexed Read Accesses
1553
Table 234. Fsmc_Bwtrx Bit Fields
1553
Figure 446. Multiplexed Write Accesses
1554
Table 235. Fsmc_Bcrx Bit Fields
1554
Table 236. Fsmc_Btrx Bit Fields
1555
Figure 447. Asynchronous Wait During a Read Access
1556
Figure 448. Asynchronous Wait During a Write Access
1557
Synchronous Transactions
1558
Figure 449. Wait Configurations
1559
Figure 450. Synchronous Multiplexed Read Mode - NOR, PSRAM (CRAM)
1560
Table 237. Fsmc_Bcrx Bit Fields
1560
Table 238. Fsmc_Btrx Bit Fields
1561
Figure 451. Synchronous Multiplexed Write Mode - PSRAM (CRAM)
1562
Table 239. Fsmc_Bcrx Bit Fields
1562
Table 240. Fsmc_Btrx Bit Fields
1563
NOR/PSRAM Control Registers
1564
NAND Flash/Pc Card Controller
1571
External Memory Interface Signals
1572
Table 241. Programmable NAND/PC Card Access Parameters
1572
Table 242. 8-Bit NAND Flash
1572
Table 243. 16-Bit NAND Flash
1573
Table 244. 16-Bit PC Card
1573
NAND Flash / PC Card Supported Memories and Transactions
1574
Table 245. Supported Memories and Transactions
1574
Figure 452. NAND/PC Card Controller Timing for Common Memory Access
1575
NAND Flash Operations
1575
Figure 453. Access to Non 'CE Don't Care' NAND-Flash
1576
NAND Flash Pre-Wait Functionality
1576
In NAND Flash Memory
1577
PC Card/Compactflash Operations
1578
Table 246. 16-Bit PC-Card Signals and Access Type
1579
NAND Flash/Pc Card Control Registers
1580
Table 247. ECC Result Relevant Bits
1586
Table 248. FSMC Register Map
1587
FMC Main Features
1589
Block Diagram
1590
Figure 454. FMC Block Diagram
1591
AHB Interface
1591
Supported Memories and Transactions
1592
External Device Address Mapping
1593
Figure 455. FMC Memory Banks
1594
NOR/PSRAM Address Mapping
1594
Table 249. NOR/PSRAM Bank Selection
1594
NAND Flash Memory/Pc Card Address Mapping
1595
Table 250. NOR/PSRAM External Memory Address
1595
Table 251. NAND/PC Card Memory Mapping and Timing Registers
1595
Table 252. NAND Bank Selection
1596
Table 253. SDRAM Bank Selection
1596
Table 254. SDRAM Address Mapping
1596
Table 255. SDRAM Address Mapping with 8-Bit Data Bus Width
1597
Table 256. SDRAM Address Mapping with 16-Bit Data Bus Width
1598
Table 257. SDRAM Address Mapping with 32-Bit Data Bus Width
1598
NOR Flash/Psram Controller
1599
External Memory Interface Signals
1600
Table 258. Programmable NOR/PSRAM Access Parameters
1600
Table 259. Non-Multiplexed I/O nor Flash Memory
1601
Table 260. 16-Bit Multiplexed I/O nor Flash Memory
1601
Table 261. Non-Multiplexed I/Os PSRAM/SRAM
1601
Supported Memories and Transactions
1602
Table 262. 16-Bit Multiplexed I/O PSRAM
1602
Table 263. nor Flash/Psram: Example of Supported Memories and Transactions
1603
General Timing Rules
1604
Figure 456. Mode1 Read Access Waveforms
1605
Figure 457. Mode1 Write Access Waveforms
1605
Table 264. Fmc_Bcrx Bit Fields
1606
Table 265. Fmc_Btrx Bit Fields
1606
Figure 458. Modea Read Access Waveforms
1607
Figure 459. Modea Write Access Waveforms
1608
Table 266. Fmc_Bcrx Bit Fields
1608
Table 267. Fmc_Btrx Bit Fields
1609
Table 268. Fmc_Bwtrx Bit Fields
1609
Figure 460. Mode2 and Mode B Read Access Waveforms
1610
Figure 461. Mode2 Write Access Waveforms
1610
Figure 462. Modeb Write Access Waveforms
1611
Table 269. Fmc_Bcrx Bit Fields
1611
Table 270. Fmc_Btrx Bit Fields
1612
Table 271. Fmc_Bwtrx Bit Fields
1612
Figure 463. Modec Read Access Waveforms
1613
Figure 464. Modec Write Access Waveforms
1613
Table 272. Fmc_Bcrx Bit Fields
1614
Table 273. Fmc_Btrx Bit Fields
1614
Figure 465. Moded Read Access Waveforms
1615
Table 274. Fmc_Bwtrx Bit Fields
1615
Figure 466. Moded Write Access Waveforms
1616
Table 275. Fmc_Bcrx Bit Fields
1616
Table 276. Fmc_Btrx Bit Fields
1617
Table 277. Fmc_Bwtrx Bit Fields
1617
Figure 467. Muxed Read Access Waveforms
1618
Figure 468. Muxed Write Access Waveforms
1618
Table 278. Fmc_Bcrx Bit Fields
1619
Table 279. Fmc_Btrx Bit Fields
1619
Figure 469. Asynchronous Wait During a Read Access Waveforms
1620
Figure 470. Asynchronous Wait During a Write Access Waveforms
1621
Synchronous Transactions
1621
Figure 471. Wait Configuration Waveforms
1623
Figure 472. Synchronous Multiplexed Read Mode Waveforms - NOR, PSRAM (CRAM)
1623
Table 280. Fmc_Bcrx Bit Fields
1624
Table 281. Fmc_Btrx Bit Fields
1624
Figure 473. Synchronous Multiplexed Write Mode Waveforms - PSRAM (CRAM)
1625
Table 282. Fmc_Bcrx Bit Fields
1625
Table 283. Fmc_Btrx Bit Fields
1626
NOR/PSRAM Controller Registers
1627
NAND Flash/Pc Card Controller
1634
External Memory Interface Signals
1635
Table 284. Programmable NAND Flash/Pc Card Access Parameters
1635
Table 285. 8-Bit NAND Flash
1635
Table 286. 16-Bit NAND Flash
1636
Table 287. 16-Bit PC Card
1636
NAND Flash / PC Card Supported Memories and Transactions
1637
Table 288. Supported Memories and Transactions
1637
Figure 474. NAND Flash/Pc Card Controller Waveforms for Common Memory Access
1638
NAND Flash Operations
1638
Figure 475. Access to Non 'CE Don't Care' NAND-Flash
1639
NAND Flash Prewait Functionality
1639
In NAND Flash Memory
1640
PC Card/Compactflash Operations
1641
Table 289. 16-Bit PC-Card Signals and Access Type
1641
NAND Flash/Pc Card Controller Registers
1642
Table 290. ECC Result Relevant Bits
1649
Table 291. SDRAM Signals
1650
SDRAM Controller
1650
SDRAM Controller Functional Description
1651
Figure 476. Burst Write SDRAM Access Waveforms
1652
Figure 477. Burst Read SDRAM Access
1653
Figure 478. Logic Diagram of Read Access with RBURST Bit Set (CAS=2, RPIPE=0)
1654
Figure 479. Read Access Crossing Row Boundary
1656
Figure 480. Write Access Crossing Row Boundary
1656
Low Power Modes
1657
Figure 481. Self-Refresh Mode
1659
Figure 482. Power-Down Mode
1660
SDRAM Controller Registers
1661
Table 292. FMC Register Map
1667
Figure 483. Block Diagram of STM32 MCU and Cortex ® -M4 with FPU-Level
1670
Debug Support
1670
Overview
1670
SWJ Debug Port (Serial Wire and JTAG)
1671
Figure 484. SWJ Debug Port
1672
Mechanism to Select the JTAG-DP or the SW-DP
1672
Table 293. SWJ Debug Port Pins
1673
Table 294. Flexible SWJ-DP Pin Assignment
1673
Internal Pull-Up and Pull-Down on JTAG Pins
1674
Using Serial Wire and Releasing the Unused Debug Pins as Gpios
1675
Figure 485. JTAG TAP Connections
1676
ID Codes and Locking Mechanism
1677
Boundary Scan TAP
1678
Table 295. JTAG Debug Port Data Registers
1678
Table 296. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
1679
Table 297. Packet Request (8-Bits)
1680
SW Debug Port
1680
SW-DP State Machine (Reset, Idle States, ID Code)
1681
Table 298. ACK Response (3 Bits)
1681
Table 299. DATA Transfer (33 Bits)
1681
DP and AP Read/Write Accesses
1682
Table 300. SW-DP Registers
1682
SW-AP Registers
1683
Table 301. Cortex
1684
Table 302. Core Debug Registers
1685
Capability of the Debugger Host to Connect under System Reset
1686
DWT (Data Watchpoint Trigger)
1687
Table 303. Main ITM Registers
1688
Table 304. Main ETM Registers
1689
ETM (Embedded Trace Macrocell)
1689
Configuration Example
1690
Debug MCU Configuration Register
1691
Debug MCU APB1 Freeze Register (DBGMCU_APB1_FZ)
1692
Debug MCU APB2 Freeze Register (DBGMCU_APB2_FZ)
1694
Figure 486. TPIU Block Diagram
1695
TPIU (Trace Port Interface Unit)
1695
Table 305. Asynchronous TRACE Pin Assignment
1696
Table 306. Synchronous TRACE Pin Assignment
1696
Table 307. Flexible TRACE Pin Assignment
1697
TPUI Formatter
1697
TPUI Frame Synchronization Packets
1698
Asynchronous Mode
1699
Table 308. Important TPIU Registers
1699
Example of Configuration
1700
Table 309. DBG Register Map and Reset Values
1700
Device Electronic Signature
1702
Flash Size
1703
Table 310. Document Revision History
1704
4
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STMicroelectronics STM32F405 Specifications
General
Brand
STMicroelectronics
Model
STM32F405
Category
Controller
Language
English
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