STMicroelectronics STM32F405

DocID018909 Rev 11 1623/1731
RM0090 Flexible memory controller (FMC)
1669
The FMC supports both NOR Flash wait state configurations, for each Chip Select, thanks
to the WAITCFG bit in the FMC_BCRx registers (x = 0..3).
Figure 471. Wait configuration waveforms
Figure 472. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)
1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access,
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