STMicroelectronics STM32F405 User Manual

Chrom-Art Accelerator™ controller (DMA2D) RM0090
348/1731 DocID018909 Rev 11
11.3.8 DMA2D output FIFO
The output FIFO programs the pixels according to the color format defined in the output
PFC.
The destination area is defined through a set of control registers:
• DMA2D output memory address register (DMA2D_OMAR)
• DMA2D output offset register (DMA2D_OOR)
• DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)
If the DMA2D operates in register-to-memory mode, the configured output rectangle is filled
by the color specified in the DMA2D output color register (DMA2D_OCOLR) which contains
a fixed 32-bit, 24-bit or 16-bit value. The format is selected by the CM[2:0] field of the
DMA2D_OPFCCR register.
The data are stored into the memory in the order defined in Table 58: Data order in memory
The RGB888 aligned on 32-bit is supported through the ARGB8888 mode.
11.3.9 DMA2D AHB master port timer
An 8-bit timer is embedded into the AHB master port to provide an optional limitation of the
bandwidth on the crossbar.
This timer is clocked by the AHB clock and counts a dead time between two consecutive
accesses. This limits the bandwidth usage.
Table 57. Supported color mode in output
CM[2:0] Color mode
000 ARGB8888
001 RGB888
010 RGB565
011 ARGB1555
100 ARGB4444
Table 58. Data order in memory
Color Mode @ + 3@ + 2@ + 1@ + 0
ARGB8888 A
0
[7:0] R
0
[7:0] G
0
[7:0] B
0
[7:0]
RGB888
B
1
[7:0] R
0
[7:0] G
0
[7:0] B
0
[7:0]
G
2
[7:0] B
2
[7:0] R
1
[7:0] G
1
[7:0]
R
3
[7:0] G
3
[7:0] B
3
[7:0] R
2
[7:0]
RGB565 R
1
[4:0]G
1
[5:3] G
1
[2:0]B
1
[4:0] R
0
[4:0]G
0
[5:3] G
0
[2:0]B
0
[4:0]
ARGB1555 A
1
[0]R
1
[4:0]G
1
[4:3] G
1
[2:0]B
1
[4:0] A
0
[0]R
0
[4:0]G
0
[4:3] G
0
[2:0]B
0
[4:0]
ARGB4444 A
1
[3:0]R
1
[3:0] G
1
[3:0]B
1
[3:0] A
0
[3:0]R
0
[3:0] G
0
[3:0]B
0
[3:0]

STMicroelectronics STM32F405 Specifications

General

Brand	STMicroelectronics
Model	STM32F405
Category	Controller
Language	English