Interrupts and events RM0090
388/1731 DocID018909 Rev 11
12.3.5 Software interrupt event register (EXTI_SWIER)
Address offset: 0x10
Reset value: 0x0000 0000
12.3.6 Pending register (EXTI_PR)
Address offset: 0x14
Reset value: undefined
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
SWIER
22
SWIER
21
SWIER
20
SWIER
19
SWIER
18
SWIER
17
SWIER
16
rw rw rw rw rw rw rw
1514131211109 8765432 1 0
SWIER
15
SWIER
14
SWIER
13
SWIER
12
SWIER
11
SWIER
10
SWIER
9
SWIER
8
SWIER
7
SWIER
6
SWIER
5
SWIER
4
SWIER
3
SWIER
2
SWIER
1
SWIER
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 SWIERx: Software Interrupt on line x
If interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is
set at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an
interrupt request generation.
This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
PR22 PR21 PR20 PR19 PR18 PR17 PR16
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
1514131211109 8765432 1 0
PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 PRx: Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line.
This bit is cleared by programming it to ‘1’.
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