DocID018909 Rev 11 1649/1731
RM0090 Flexible memory controller (FMC)
1669
ECC result registers 2/3 (FMC_ECCR2/3)
Address offset: 0x54 + 0x20 * (x – 1), x = 2 or 3
Reset value: 0x0000 0000
These registers contain the current error correction code value computed by the ECC
computation modules of the FMC controller (one module per NAND Flash memory bank).
When the CPU reads the data from a NAND Flash memory page at the correct address
(refer to Section 37.6.6: Computation of the error correction code (ECC) in NAND Flash
memory), the data read/written from/to the NAND Flash memory are processed
automatically by the ECC computation module. When X byte have been read (according to
the ECCPS field in the FMC_PCRx registers), the CPU must read the computed ECC value
from the FMC_ECCx registers. It then verifies if these computed parity data are the same as
the parity value recorded in the spare area, to determine whether a page is valid, and, to
correct it otherwise. The FMC_ECCRx registers should be cleared after being read by
setting the ECCEN bit to ‘0’. To compute a new data block, the ECCEN bit must be set to ’1’.
313029282726252423222120191817161514131211109876543210
ECC[31:0]
r
Bits 31:0 ECC[31:0]: ECC result
This field contains the value computed by the ECC computation logic. Table 290 describes the
contents of these bit fields.
Table 290. ECC result relevant bits
ECCPS[2:0] Page size in byte ECC bits
000 256 ECC[21:0]
001 512 ECC[23:0]
010 1024 ECC[25:0]
011 2048 ECC[27:0]
100 4096 ECC[29:0]
101 8192 ECC[31:0]
To Next Page
Loading...
Need help?
General
