Flexible memory controller (FMC) RM0090
1612/1731 DocID018909 Rev 11
Note: The FMC_BWTRx register is valid only if the extended mode is set (mode B), otherwise its
content is don’t care.
5-4 MWID As needed
3-2 MTYP[1:0] 0x2 (NOR Flash memory)
1 MUXEN 0x0
0 MBKEN 0x1
Table 270. FMC_BTRx bit fields
Bit number Bit name Value to set
31-30 Reserved 0x0
29-28 ACCMOD 0x1 if extended mode is set
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the access second phase (DATAST HCLK cycles) for
read accesses.
7-4 ADDHLD Don’t care
3-0 ADDSET[3:0]
Duration of the access first phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 0.
Table 271. FMC_BWTRx bit fields
Bit number Bit name Value to set
31-30 Reserved 0x0
29-28 ACCMOD 0x1 if extended mode is set
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the access second phase (DATAST HCLK cycles) for
write accesses.
7-4 ADDHLD Don’t care
3-0 ADDSET[3:0]
Duration of the access first phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 0.
Table 269. FMC_BCRx bit fields (continued)
Bit
number
Bit name Value to set
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