Serial peripheral interface (SPI) RM0090
900/1731 DocID018909 Rev 11
PCM standard
For the PCM standard, there is no need to use channel-side information. The two PCM
modes (short and long frame) are available and configurable using the PCMSYNC bit in
SPI_I2SCFGR.
Figure 279. PCM standard waveforms (16-bit)
For long frame synchronization, the WS signal assertion time is fixed 13 bits in master
mode.
For short frame synchronization, the WS synchronization signal is only one cycle long.
Figure 280. PCM standard waveforms (16-bit extended to 32-bit packet frame)
Note: For both modes (master and slave) and for both synchronizations (short and long), the
number of bits between two consecutive pieces of data (and so two synchronization signals)
needs to be specified (DATLEN and CHLEN bits in the SPI_I2SCFGR register) even in
slave mode.
MSB
LSB
MSB
CK
WS
SD
16-bit
WS
fixed to 13-bit
short
frame
long
frame
MSB
CK
WS
SD
16-bit
WS
fixed to 13-bit
short
frame
long
frame
LSB
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