DocID018909 Rev 11 149/1731
RM0090 Power controller (PWR)
149
5.6 PWR register map
The following table summarizes the PWR registers.
Refer to Table 1 on page 64 for the register boundary addresses.
Table 31. PWR - register map and reset values for STM32F405xx/07xx and STM32F415xx/17xx
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x000
PWR_CR
Reserved
VOS
Reserved
FPDS
DBP
PLS[2:0]
PVDE
CSBF
CWUF
PDDS
LPDS
Reset value 1 0000000000
0x004
PWR_CSR
Reserved
VOSRDY
Reserved
BRE
EWUP
Reserved
BRR
PVDO
SBF
WUF
Reset value 0 00 0000
Table 32. PWR - register map and reset values for STM32F42xxx and STM32F43xxx
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x000
PWR_CR
Reserved
UDEN[1:0]
ODSWEN
ODEN
VOS[1:0]
ADCDC1
Reserved
MRUDS
LPUDS
FPDS
DBP
PLS[2:0]
PVDE
CSBF
CWUF
PDDS
LPDS
Reset value 1111110 110000000000
0x004
PWR_CSR
Reserved
UDRDY[1:0]
ODSWRDY
ODRDY
Reserved
VOSRDY
Reserved
BRE
EWUP
Reserved
BRR
PVDO
SBF
WUF
Reset value 0000 0 00 0000