STMicroelectronics STM32F405 User Manual

USB on-the-go high-speed (OTG_HS) RM0090
1458/1731 DocID018909 Rev 11
35.12.5 OTG_HS power and clock gating control register
(OTG_HS_PCGCCTL)
Address offset: 0xE00
Reset value: 0x0000 0000
This register is available in host and peripheral modes.
35.12.6 OTG_HS register map
The table below gives the USB OTG register map and reset values.
3130 29282726252423222120191817161514131211109876543210
Reserved
PHYSUSP
Reserved
GATEHCLK
STPPCLK
rw rw rw
Bit 31:5 Reserved, must be kept at reset value.
Bit 4 PHYSUSP: PHY suspended
Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended
after the application has set the STPPCLK bit (bit 0).
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 GATEHCLK: Gate HCLK
The application sets this bit to gate HCLK to modules other than the AHB Slave and Master
and wakeup logic when the USB is suspended or the session is not valid. The application
clears this bit when the USB is resumed or a new session starts.
Bit 0 STPPCLK: Stop PHY clock
The application sets this bit to stop the PHY clock when the USB is suspended, the session
is not valid, or the device is disconnected. The application clears this bit when the USB is
resumed or a new session starts.
Table 210. OTG_HS register map and reset values
Offset Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
11
10
9 8 7 6 5 4 3 2 1 0
0x000
OTG_HS_GO
TGCTL
Reserved
BSVLD ASVLD
DBCT
CIDSTS
Reserved
DHNPEN
HSHNPEN
HNPRQ
HNGSCS
Reserved
SRQ
SRQSCS
Reset value 0 0 0 1 0 0 0 0 0 0
0x004
OTG_HS_GO
TGINT
Reserved
DBCDNE
ADTOCHG
HNGDET
Reserved
HNSSCHG
SRSSCHG
Reserved
SEDET
Res.
Reset value 0 0 0 0 0 0
0x008
OTG_HS_GA
HBCFG
Reserved
PTXFELVL
TXFELVL
Reserved
GINT
Reset value 00 0

STMicroelectronics STM32F405 Specifications

General

Brand	STMicroelectronics
Model	STM32F405
Category	Controller
Language	English