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DocID018909 Rev 11 1553/1731

RM0090 Flexible static memory controller (FSMC)

1588

Muxed mode - multiplexed asynchronous access to NOR Flash memory

Figure 445. Multiplexed read accesses

Table 234. FSMC_BWTRx bit fields

Bit No. Bit name Value to set

31:30 Reserved 0x0

29-28 ACCMOD 0x3

27-24 DATLAT 0x0

23-20 CLKDIV 0x0

19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)

15-8 DATAST

Duration of the second access phase (DATAST+1 HCLK cycles) for

write accesses

7-4 ADDHLD

Duration of the middle phase of the write access (ADDHLD HCLK

cycles)

3-0 ADDSET[3:0]

Duration of the first access phase (ADDSET+1 HCLK cycles) for

write accesses. Minimum value for ADDSET is 0.

A[25:16]

NOE

ADDSET DATAST

Memory transaction

NEx

AD[15:0]

HCLK cycles HCLK cycles

NWE

NADV

data driven

by memory

ai15568

High

ADDHLD

HCLK cycles

Lower address

Default Chapter2
- Table of Contents2
Documentation Conventions57
- List of Abbreviations for Registers57
- Glossary58
- Peripheral Availability58
Memory and Bus Architecture59
- System Architecture59
- Memory Organization64
- Memory Map64
- Boot Configuration69
- Table 2. Boot Modes69
- Table 3. Memory Mapping Vs. Boot Mode/Physical Remap in Stm32F405Xx/07Xx and Stm32F415Xx/17Xx71
- Table 4. Memory Mapping Vs. Boot Mode/Physical Remap in Stm32F42Xxx and Stm32F43Xxx71
Embedded Flash Memory Interface73
- Introduction73
- Main Features73
- Figure 3. Flash Memory Interface Connection Inside System Architecture (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)73
- Embedded Flash Memory in Stm32F405Xx/07Xx and Stm32F415Xx/17Xx74
- Figure 4. Flash Memory Interface Connection Inside System Architecture (Stm32F42Xxx and Stm32F43Xxx)74
- Table 5. Flash Module Organization (Stm32F40X and Stm32F41X)75
- Embedded Flash Memory in Stm32F42Xxx and Stm32F43Xxx76
  - Table 6. Flash Module - 2 Mbyte Dual Bank Organization (Stm32F42Xxx and Stm32F43Xxx)77
  - Mbyte Flash Memory Single Bank Vs Dual Bank Organization (Stm32F42Xxx and Stm32F43Xxx)78
- Mbyte Single Bank Flash Memory Organization (Stm32F42Xxx and Stm32F43Xxx)78
- Table 9. 1 Mbyte Dual Bank Flash Memory Organization (Stm32F42Xxx and Stm32F43Xxx)79
- Read Interface80
- Erase and Program Operations84
- Option Bytes88
- One-Time Programmable Bytes97
- Table 18. OTP Area Organization97
- Flash Interface Registers98
CRC Calculation Unit113
- CRC Introduction113
- CRC Main Features113
- Figure 8. CRC Calculation Unit Block Diagram113
- CRC Functional Description114
- CRC Registers114
Power Controller (PWR)116
- Power Supplies116
- Power Supply Supervisor124
- Low-Power Modes126
- Power Control Registers (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)141
  - PWR Power Control Register (PWR_CR)141
    - For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx141
  - PWR Power Control/Status Register (PWR_CSR)142
    - For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx142
- Power Control Registers (Stm32F42Xxx and Stm32F43Xxx)144
  - PWR Power Control Register (PWR_CR)144
    - For Stm32F42Xxx and Stm32F43Xxx144
  - PWR Power Control/Status Register (PWR_CSR)147
    - For Stm32F42Xxx and Stm32F43Xxx147
- PWR Register Map149
- Table 31. PWR - Register Map and Reset Values for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx149
- Table 32. PWR - Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx149
Reset and Clock Control for Stm32F42Xxx and Stm32F43Xxx (RCC)150
- Reset150
- Clocks151
- RCC Registers161
Reset and Clock Control for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC)213
- Reset213
- Clocks215
- RCC Registers224
General-Purpose I/Os (GPIO)269
- GPIO Introduction269
- GPIO Main Features269
- GPIO Functional Description269
- GPIO Registers283
System Configuration Controller (SYSCFG)291
- I/O Compensation Cell291
- SYSCFG Registers for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx291
  - SYSCFG Memory Remap Register (SYSCFG_MEMRMP)291
  - SYSCFG Peripheral Mode Configuration Register (SYSCFG_PMC)292
  - SYSCFG External Interrupt Configuration Register 1293
    - (Syscfg_Exticr1)293
    - (Syscfg_Exticr2)293
  - SYSCFG External Interrupt Configuration Register 3294
    - (Syscfg_Exticr3)294
  - Compensation Cell Control Register (SYSCFG_CMPCR)295
  - Table 40. SYSCFG Register Map and Reset Values (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)296
  - SYSCFG Peripheral Mode Configuration Register (SYSCFG_PMC)298
  - SYSCFG External Interrupt Configuration Register299
  - SYSCFG External Interrupt Configuration Register300
  - Compensation Cell Control Register (SYSCFG_CMPCR)302
  - Table 41. SYSCFG Register Map and Reset Values (Stm32F42Xxx and Stm32F43Xxx)303
  - SYSCFG Register Maps for Stm32F42Xxx and Stm32F43Xxx303
- DMA Introduction304
- Figure 32. DMA Block Diagram306
- DMA Functional Description306
  - Figure 33. System Implementation of the Two DMA Controllers (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx )307
  - DMA Transactions308
  - Figure 34. System Implementation of the Two DMA Controllers (Stm32F42Xxx and Stm32F43Xxx)308
  - Figure 35. Channel Selection309
  - Table 42. DMA1 Request Mapping309
  - Arbiter310
  - Table 43. DMA2 Request Mapping310
  - DMA Streams311
  - Table 44. Source and Destination Address311
  - Figure 36. Peripheral-To-Memory Mode312
  - Figure 37. Memory-To-Peripheral Mode313
  - Figure 38. Memory-To-Memory Mode314
  - Pointer Incrementation314
  - Circular Mode315
  - Programmable Data Width, Packing/Unpacking, Endianess316
  - Table 45. Source and Destination Address Registers in Double Buffer Mode (DBM=1)316
  - Table 46. Packing/Unpacking & Endian Behavior (Bit PINC = MINC = 1)317
  - Single and Burst Transfers318
  - Table 47. Restriction on NDT Versus PSIZE and MSIZE318
  - Figure 39. FIFO Structure319
  - Table 48. FIFO Threshold Configurations320
  - DMA Transfer Completion321
  - DMA Transfer Suspension322
  - Flow Controller323
  - Summary of the Possible DMA Configurations324
  - Table 49. Possible DMA Configurations324
  - Error Management325
  - DMA Interrupts326
  - Table 50. DMA Interrupt Requests326
- DMA Registers327
  - DMA High Interrupt Status Register (DMA_HISR)328
  - DMA Low Interrupt Flag Clear Register (DMA_LIFCR)329
  - DMA Stream X Configuration Register (Dma_Sxcr) (X = 0..7)330
  - DMA Stream X Number of Data Register (Dma_Sxndtr) (X = 0..7)333
  - DMA Stream X Peripheral Address Register (Dma_Sxpar) (X = 0..7)334
  - DMA Stream X FIFO Control Register (Dma_Sxfcr) (X = 0..7)335
  - Table 51. DMA Register Map and Reset Values337
- DMA2D Introduction341
- DMA2D Main Features342
  - DMA2D Control343
  - Table 52. Supported Color Mode in Input344
  - DMA2D Foreground and Background Pixel Format Converter (PFC)344
  - Table 53. Data Order in Memory345
  - DMA2D Foreground and Background CLUT Interface346
  - Table 56. CLUT Data Order in Memory347
  - DMA2D Blender347
  - Table 57. Supported Color Mode in Output348
  - Table 58. Data Order in Memory348
  - DMA2D Output FIFO348
  - DMA2D Transactions349
  - DMA2D Transfer Control (Start, Suspend, Abort and Completion)352
  - Table 59. DMA2D Interrupt Requests353
  - Watermark353
- DMA2D Registers354
  - DMA2D Interrupt Status Register (DMA2D_ISR)356
  - DMA2D Interrupt Flag Clear Register (DMA2D_IFCR)357
  - DMA2D Foreground Memory Address Register (DMA2D_FGMAR)358
  - DMA2D Background Memory Address Register (DMA2D_BGMAR)359
  - DMA2D Foreground Color Register (DMA2D_FGCOLR)362
  - DMA2D Background PFC Control Register (DMA2D_BGPFCCR)363
  - DMA2D Background Color Register (DMA2D_BGCOLR)365
  - DMA2D Output PFC Control Register (DMA2D_OPFCCR)366
  - DMA2D Output Color Register (DMA2D_OCOLR)367
  - DMA2D Output Memory Address Register (DMA2D_OMAR)368
  - DMA2D Output Offset Register (DMA2D_OOR)369
  - DMA2D Line Watermark Register (DMA2D_LWR)370
  - Table 60. DMA2D Register Map and Reset Values371
- Nested Vectored Interrupt Controller (NVIC)373
  - Table 61. Vector Table for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx374
  - Table 62. Vector Table for Stm32F42Xxx and Stm32F43Xxx377
  - EXTI Main Features381
  - EXTI Block Diagram382
  - Figure 41. External Interrupt/Event Controller Block Diagram382
  - Figure 42. External Interrupt/Event GPIO Mapping (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)384
  - Figure 43. External Interrupt/Event GPIO Mapping (Stm32F42Xxx and Stm32F43Xxx)385
  - Interrupt Mask Register (EXTI_IMR)386
  - Rising Trigger Selection Register (EXTI_RTSR)387
  - Software Interrupt Event Register (EXTI_SWIER)388
  - EXTI Register Map389
  - Table 63. External Interrupt/Event Controller Register Map and Reset Values389
  - Table 64. External Interrupt/Event Controller Register Map and Reset Values389
- ADC Introduction390
- ADC Functional Description391
  - Figure 44. Single ADC Block Diagram392
  - ADC On-Off Control393
  - Table 65. ADC Pins393
  - Single Conversion Mode394
  - Continuous Conversion Mode395
  - Figure 45. Timing Diagram395
  - Figure 46. Analog Watchdog's Guarded Area396
  - Scan Mode396
  - Table 66. Analog Watchdog Channel Selection396
  - Figure 47. Injected Conversion Latency397
  - Injected Channel Management397
  - Discontinuous Mode398
  - Figure 48. Right Alignment of 12-Bit Data399
  - Figure 49. Left Alignment of 12-Bit Data399
  - Figure 50. Left Alignment of 6-Bit Data399
  - Table 67. Configuring the Trigger Polarity400
- Channel-Wise Programmable Sampling Time400
- Table 68. External Trigger for Regular Channels401
- Table 69. External Trigger for Injected Channels402
- Fast Conversion Mode402
- Data Management403
  - Conversions Without DMA and Without Overrun Detection404
  - Figure 51. Multi ADC Block Diagram (1)405
  - Injected Simultaneous Mode407
  - Figure 52. Injected Simultaneous Mode on 4 Channels: Dual ADC Mode408
  - Figure 53. Injected Simultaneous Mode on 4 Channels: Triple ADC Mode408
  - Regular Simultaneous Mode408
  - Figure 54. Regular Simultaneous Mode on 16 Channels: Dual ADC Mode409
  - Figure 55. Regular Simultaneous Mode on 16 Channels: Triple ADC Mode409
  - Figure 56. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Dual ADC Mode410
  - Figure 57. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Triple ADC Mode411
  - Alternate Trigger Mode411
  - Figure 58. Alternate Trigger: Injected Group of each ADC412
  - Figure 59. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Mode413
  - Figure 60. Alternate Trigger: Injected Group of each ADC413
  - Combined Regular/Injected Simultaneous Mode413
  - Figure 61. Alternate + Regular Simultaneous414
  - Combined Regular Simultaneous + Alternate Trigger Mode414
  - Figure 62. Case of Trigger Occurring During Injected Conversion415
- Temperature Sensor415
- Figure 63. Temperature Sensor and VREFINT Channel Block Diagram416
- Table 70. ADC Interrupts417
- Battery Charge Monitoring417
- ADC Registers418
  - ADC Control Register 1 (ADC_CR1)419
  - ADC Control Register 2 (ADC_CR2)421
  - ADC Sample Time Register 1 (ADC_SMPR1)423
  - ADC Injected Channel Data Offset Register X (Adc_Jofrx) (X=1..4)424
  - ADC Watchdog Lower Threshold Register (ADC_LTR)425
  - ADC Regular Sequence Register 2 (ADC_SQR2)426
  - ADC Injected Sequence Register (ADC_JSQR)427
  - ADC Regular Data Register (ADC_DR)428
  - ADC Common Control Register (ADC_CCR)429
  - Table 71. ADC Global Register Map432
  - Table 72. ADC Register Map and Reset Values for each ADC432
  - Table 73. ADC Register Map and Reset Values (Common ADC Registers)434
Digital-To-Analog Converter (DAC)435
- Table 74. DAC Pins436
- Figure 64. DAC Channel Block Diagram436
- DAC Functional Description437
- Dual DAC Channel Conversion442
- DAC Registers447
Digital Camera Interface (DCMI)457
- Figure 72. DCMI Block Diagram458
- Figure 73. Top-Level Block Diagram458
- DCMI Functional Overview458
- Data Format Description466
- Table 84. Data Storage in RGB Progressive Video Format467
- Table 85. Data Storage in Ycbcr Progressive Video Format467
- Table 86. DCMI Interrupts467
- DCMI Register Description468
LCD-TFT Controller (LTDC)480
- Figure 81. LTDC Block Diagram481
- LTDC Functional Description481
- Table 88. LCD-TFT Pins and Signal Interface482
- Figure 82. LCD-TFT Synchronous Timings483
- Figure 83. Layer Window Programmable Parameters485
- Table 89. Pixel Data Mapping Versus Color Format486
- Figure 84. Blending Two Layers with Background488
- Figure 85. Interrupt Events489
- LTDC Interrupts489
- Table 90. LTDC Interrupt Requests490
- LTDC Programming Procedure490
- LTDC Registers491
  - LTDC Active Width Configuration Register (LTDC_AWCR)492
  - LTDC Total Width Configuration Register (LTDC_TWCR)493
  - LTDC Shadow Reload Configuration Register (LTDC_SRCR)495
  - LTDC Interrupt Enable Register (LTDC_IER)496
  - LTDC Interrupt Status Register (LTDC_ISR)497
  - LTDC Line Interrupt Position Configuration Register (LTDC_LIPCR)498
  - LTDC Current Display Status Register (LTDC_CDSR)499
  - LTDC Layerx Control Register (Ltdc_Lxcr) (Where X=1..2)500
    - Ltdc_Lxwvpcr) (Where X=1..2)501
  - Ltdc_Lxcfblnr) (Where X=1..2)507
    - Table 91. LTDC Register Map and Reset Values509
    - TIM1&TIM8 Introduction512
    - TIM1&TIM8 Main Features513
  - Figure 86. Advanced-Control Timer Block Diagram514
  - TIM1&TIM8 Functional Description515
  - Figure 87. Counter Timing Diagram with Prescaler Division Change from 1 to 2516
  - Figure 88. Counter Timing Diagram with Prescaler Division Change from 1 to 4516
  - Counter Modes516
  - Figure 89. Counter Timing Diagram, Internal Clock Divided by 1517
  - Figure 90. Counter Timing Diagram, Internal Clock Divided by 2517
  - Figure 91. Counter Timing Diagram, Internal Clock Divided by 4518
  - Figure 92. Counter Timing Diagram, Internal Clock Divided by N518
  - Figure 93. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)518
  - Figure 94. Counter Timing Diagram, Update Event When ARPE=1519
  - (Timx_Arr Preloaded)519
  - Figure 95. Counter Timing Diagram, Internal Clock Divided by 1520
  - Figure 96. Counter Timing Diagram, Internal Clock Divided by 2520
  - Figure 97. Counter Timing Diagram, Internal Clock Divided by 4520
  - Figure 98. Counter Timing Diagram, Internal Clock Divided by N521
  - Figure 99. Counter Timing Diagram, Update Event When Repetition Counter521
  - Is Not Used521
  - Figure 100. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6522
  - Figure 101. Counter Timing Diagram, Internal Clock Divided by 2523
  - Figure 102. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36523
  - Figure 103. Counter Timing Diagram, Internal Clock Divided by N523
  - Figure 104. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)524
  - Figure 105. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)524
- Repetition Counter524
- Figure 106. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings525
- Figure 107. Control Circuit in Normal Mode, Internal Clock Divided by 1526
- Figure 108. TI2 External Clock Connection Example526
- Clock Selection526
- Figure 109. Control Circuit in External Clock Mode 1527
- Figure 110. External Trigger Input Block528
- Figure 111. Control Circuit in External Clock Mode 2528
- Capture/Compare Channels528
- Figure 112. Capture/Compare Channel (Example: Channel 1 Input Stage)529
- Figure 113. Capture/Compare Channel 1 Main Circuit529
- Figure 114. Output Stage of Capture/Compare Channel (Channel 1 to 3)530
- Figure 115. Output Stage of Capture/Compare Channel (Channel 4)530
- Input Capture Mode530
- Figure 116. PWM Input Mode Timing532
- Forced Output Mode533
- Figure 117. Output Compare Mode, Toggle on OC1534
- PWM Mode534
- Figure 118. Edge-Aligned PWM Waveforms (ARR=8)535
- Figure 119. Center-Aligned PWM Waveforms (ARR=8)536
- Complementary Outputs and Dead-Time Insertion537
- Figure 120. Complementary Output with Dead-Time Insertion538
- Figure 121. Dead-Time Waveforms with Delay Greater than the Negative Pulse538
- Figure 122. Dead-Time Waveforms with Delay Greater than the Positive Pulse538
- Using the Break Function539
- Figure 123. Output Behavior in Response to a Break541
- Figure 124. Clearing Timx Ocxref542
- Clearing the Ocxref Signal on an External Event542
- Figure 125. 6-Step Generation, COM Example (OSSR=1)543
- Step PWM Generation543
- Figure 126. Example of One Pulse Mode544
- Encoder Interface Mode545
- Table 92. Counting Direction Versus Encoder Signals546
- Figure 127. Example of Counter Operation in Encoder Interface Mode547
- Figure 128. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted547
- Timer Input XOR Function547
- Interfacing with Hall Sensors548
- Figure 129. Example of Hall Sensor Interface549
- Figure 130. Control Circuit in Reset Mode550
- Timx and External Trigger Synchronization550
  - Figure 131. Control Circuit in Gated Mode551
  - Timer Synchronization553
  - TIM1&TIM8 Registers554
  - TIM1&TIM8 Control Register 2 (Timx_Cr2)555
  - TIM1&TIM8 Slave Mode Control Register (Timx_Smcr)558
- TIM2 to TIM5 Introduction582
- Figure 134. General-Purpose Timer Block Diagram583
- TIM2 to TIM5 Functional Description583
- Figure 135. Counter Timing Diagram with Prescaler Division Change from 1 to 2584
- Figure 136. Counter Timing Diagram with Prescaler Division Change from 1 to 4585
- Counter Modes585
  - Figure 137. Counter Timing Diagram, Internal Clock Divided by 1586
  - Figure 138. Counter Timing Diagram, Internal Clock Divided by 2586
  - Figure 139. Counter Timing Diagram, Internal Clock Divided by 4586
  - Figure 140. Counter Timing Diagram, Internal Clock Divided by N587
  - Figure 141. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)587
  - Figure 142. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)588
  - Figure 143. Counter Timing Diagram, Internal Clock Divided by 1589
  - Figure 144. Counter Timing Diagram, Internal Clock Divided by 2589
  - Figure 145. Counter Timing Diagram, Internal Clock Divided by 4589
  - Figure 146. Counter Timing Diagram, Internal Clock Divided by N590
  - Figure 147. Counter Timing Diagram, Update Event590
  - Figure 148. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6591
  - Figure 149. Counter Timing Diagram, Internal Clock Divided by 2592
  - Figure 150. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36592
  - Figure 151. Counter Timing Diagram, Internal Clock Divided by N592
  - Clock Selection593
  - Figure 152. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)593
  - Figure 153. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)593
  - Figure 154. Control Circuit in Normal Mode, Internal Clock Divided by 1594
  - Figure 155. TI2 External Clock Connection Example594
  - Figure 156. Control Circuit in External Clock Mode 1595
  - Figure 157. External Trigger Input Block595
  - Capture/Compare Channels596
  - Figure 158. Control Circuit in External Clock Mode 2596
  - Figure 159. Capture/Compare Channel (Example: Channel 1 Input Stage)597
  - Figure 160. Capture/Compare Channel 1 Main Circuit597
  - Figure 161. Output Stage of Capture/Compare Channel (Channel 1)598
  - Input Capture Mode598
  - PWM Input Mode599
  - Figure 162. PWM Input Mode Timing600
  - Forced Output Mode600
  - Output Compare Mode601
  - Figure 163. Output Compare Mode, Toggle on OC1602
  - PWM Mode602
  - Figure 164. Edge-Aligned PWM Waveforms (ARR=8)603
  - Figure 165. Center-Aligned PWM Waveforms (ARR=8)604
  - Figure 166. Example of One-Pulse Mode605
  - Clearing the Ocxref Signal on an External Event606
  - Encoder Interface Mode607
  - Figure 167. Clearing Timx Ocxref607
  - Figure 168. Example of Counter Operation in Encoder Interface Mode608
  - Table 96. Counting Direction Versus Encoder Signals608
  - Figure 169. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted609
  - Timer Input XOR Function609
  - Figure 170. Control Circuit in Reset Mode610
  - Figure 171. Control Circuit in Gated Mode611
  - Figure 172. Control Circuit in Trigger Mode611
  - Figure 173. Control Circuit in External Clock Mode 2 + Trigger Mode612
  - Timer Synchronization612
  - Figure 174. Master/Slave Timer Example613
  - Figure 175. Gating Timer 2 with OC1REF of Timer 1614
  - Figure 176. Gating Timer 2 with Enable of Timer 1615
  - Figure 177. Triggering Timer 2 with Update of Timer 1615
  - Figure 178. Triggering Timer 2 with Enable of Timer 1616
  - Debug Mode617
  - Figure 179. Triggering Timer 1 and 2 with Timer 1 TI1 Input617
- TIM2 to TIM5 Registers618
  - Timx Control Register 2 (Timx_Cr2)620
  - Timx Slave Mode Control Register (Timx_Smcr)621
  - Table 97. Timx Internal Trigger Connection623
  - Timx Dma/Interrupt Enable Register (Timx_Dier)623
  - Timx Status Register (Timx_Sr)624
  - Timx Event Generation Register (Timx_Egr)626
  - Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)627
  - Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)630
  - Timx Capture/Compare Enable Register (Timx_Ccer)631
  - Table 98. Output Control Bit for Standard Ocx Channels632
  - Timx Counter (Timx_Cnt)633
  - Timx Capture/Compare Register 1 (Timx_Ccr1)634
  - Timx Capture/Compare Register 3 (Timx_Ccr3)635
  - Timx DMA Control Register (Timx_Dcr)636
  - TIM2 Option Register (TIM2_OR)637
  - TIM5 Option Register (TIM5_OR)638
  - Table 99. TIM2 to TIM5 Register Map and Reset Values639
  - Timx Register Map639
- TIM9 to TIM14 Introduction641
  - Figure 180. General-Purpose Timer Block Diagram (TIM9 and TIM12)642
  - TIM10/TIM11 and TIM13/TIM14 Main Features642
  - Figure 181. General-Purpose Timer Block Diagram (TIM10/11/13/14)643
- TIM9 to TIM14 Functional Description644
  - Counter Modes645
  - Figure 182. Counter Timing Diagram with Prescaler Division Change from 1 to 2645
  - Figure 183. Counter Timing Diagram with Prescaler Division Change from 1 to 4645
  - Figure 184. Counter Timing Diagram, Internal Clock Divided by 1646
  - Figure 185. Counter Timing Diagram, Internal Clock Divided by 2646
  - Figure 186. Counter Timing Diagram, Internal Clock Divided by 4647
  - Figure 187. Counter Timing Diagram, Internal Clock Divided by N647
  - Preloaded)647
  - Clock Selection648
  - Preloaded)648
  - Figure 190. Control Circuit in Normal Mode, Internal Clock Divided by 1649
  - Figure 191. TI2 External Clock Connection Example649
  - Capture/Compare Channels650
  - Figure 192. Control Circuit in External Clock Mode 1650
  - Figure 193. Capture/Compare Channel (Example: Channel 1 Input Stage)650
  - Figure 194. Capture/Compare Channel 1 Main Circuit651
  - Figure 195. Output Stage of Capture/Compare Channel (Channel 1)651
  - Input Capture Mode651
    - Figure 196. PWM Input Mode Timing653
    - PWM Input Mode (Only for TIM9/12)653
    - Forced Output Mode654
  - Figure 197. Output Compare Mode, Toggle on OC1655
  - PWM Mode655
  - Figure 198. Edge-Aligned PWM Waveforms (ARR=8)656
  - One-Pulse Mode656
  - Figure 199. Example of One Pulse Mode657
  - Figure 200. Control Circuit in Reset Mode658
  - TIM9/12 External Trigger Synchronization658
  - Figure 201. Control Circuit in Gated Mode659
  - Figure 202. Control Circuit in Trigger Mode660
  - Timer Synchronization (TIM9/12)660
- TIM9 and TIM12 Registers661
  - TIM9/12 Slave Mode Control Register (Timx_Smcr)663
  - Table 100. Timx Internal Trigger Connection664
  - TIM9/12 Interrupt Enable Register (Timx_Dier)664
  - TIM9/12 Status Register (Timx_Sr)666
  - TIM9/12 Event Generation Register (Timx_Egr)667
  - TIM9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)669
  - TIM9/12 Capture/Compare Enable Register (Timx_Ccer)672
  - Table 101. Output Control Bit for Standard Ocx Channels673
  - TIM9/12 Counter (Timx_Cnt)673
  - TIM9/12 Capture/Compare Register 1 (Timx_Ccr1)674
  - Table 102. TIM9/12 Register Map and Reset Values675
- TIM10/11/13/14 Registers677
  - TIM10/11/13/14 Interrupt Enable Register (Timx_Dier)678
  - TIM10/11/13/14 Event Generation Register (Timx_Egr)679
  - TIM10/11/13/14 Capture/Compare Mode Register680
  - Table 103. Output Control Bit for Standard Ocx Channels683
  - TIM10/11/13/14 Counter (Timx_Cnt)684
  - TIM10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)685
  - Figure 204. Counter Timing Diagram with Prescaler Division Change from 1 to 2690
  - Figure 205. Counter Timing Diagram with Prescaler Division Change from 1 to 4690
  - Counting Mode690
  - Figure 206. Counter Timing Diagram, Internal Clock Divided by 1691
  - Figure 207. Counter Timing Diagram, Internal Clock Divided by 2691
  - Figure 208. Counter Timing Diagram, Internal Clock Divided by 4692
  - Figure 209. Counter Timing Diagram, Internal Clock Divided by N692
  - Preloaded)692
  - Preloaded)693
  - Figure 212. Control Circuit in Normal Mode, Internal Clock Divided by 1693
  - Clock Source693
  - Table 105. TIM6&TIM7 Register Map and Reset Values698
Independent Watchdog (IWDG)699
- Table 106. Min/Max IWDG Timeout Period at 32 Khz (LSI)700
- Figure 213. Independent Watchdog Block Diagram700
- Debug Mode700
- IWDG Registers701
  - Reload Register (IWDG_RLR)702
  - Table 107. IWDG Register Map and Reset Values703
Window Watchdog (WWDG)704
- Figure 214. Watchdog Block Diagram705
- Figure 215. Window Watchdog Timing Diagram706
- How to Program the Watchdog Timeout706
- Table 108. Minimum and Maximum Timeout Values at 30 Mhz707
- Pclk1 )707
- Debug Mode707
- WWDG Registers708
  - Configuration Register (WWDG_CFR)709
  - Table 109. WWDG Register Map and Reset Values710
  - Table 110. Number of Cycles Required to Process each 128-Bit Block711
  - (Stm32F415/417Xx)711
  - (Stm32F43Xxx)711
- CRYP Introduction711
- Figure 216. Block Diagram (Stm32F415/417Xx)713
- CRYP Functional Description713
  - DES/TDES Cryptographic Core714
  - Figure 217. Block Diagram (Stm32F43Xxx)714
  - Figure 218. DES/TDES-ECB Mode Encryption716
  - Figure 219. DES/TDES-ECB Mode Decryption716
  - Figure 220. DES/TDES-CBC Mode Encryption718
  - AES Cryptographic Core719
  - Figure 221. DES/TDES-CBC Mode Decryption719
  - Figure 222. AES-ECB Mode Encryption720
  - Figure 223. AES-ECB Mode Decryption721
  - Figure 224. AES-CBC Mode Encryption722
  - Figure 225. AES-CBC Mode Decryption723
  - Figure 226. AES-CTR Mode Encryption724
  - Figure 227. AES-CTR Mode Decryption725
  - Figure 228. Initial Counter Block Structure for the Counter Mode725
  - Data Type730
  - Table 112. Data Types731
  - Figure 229. 64-Bit Block Construction According to DATATYPE732
  - Initialization Vectors - CRYP_IV0...1(L/R)733
  - CRYP Busy State734
  - Figure 230. Initialization Vectors Use in the TDES-CBC Encryption734
  - Procedure to Perform an Encryption or a Decryption735
  - Context Swapping736
- CRYP Interrupts738
- Figure 231. CRYP Interrupt Mapping Diagram739
- CRYP DMA Interface739
  - CRYP Control Register (CRYP_CR) for Stm32F415/417Xx741
  - CRYP Status Register (CRYP_SR)744
  - CRYP Data Input Register (CRYP_DIN)745
  - CRYP Data Output Register (CRYP_DOUT)746
  - CRYP DMA Control Register (CRYP_DMACR)747
  - CRYP Raw Interrupt Status Register (CRYP_RISR)748
  - CRYP Key Registers (CRYP_K0...3(L/R)R)749
  - CRYP Initialization Vector Registers (CRYP_IV0...1(L/R)R)751
  - CRYP Context Swap Registers (CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R) for Stm32F42Xxx and Stm32F43Xxx753
  - Table 113. CRYP Register Map and Reset Values for Stm32F415/417Xx754
  - Table 114. CRYP Register Map and Reset Values for Stm32F43Xxx755
  - Figure 232. Block Diagram758
- RNG Introduction758
  - Operation759
  - RNG Control Register (RNG_CR)760
  - RNG Data Register (RNG_DR)761
  - Table 115. RNG Register Map and Reset Map762
- HASH Introduction763
- Figure 233. Block Diagram for Stm32F415/417Xx764
- HASH Functional Description764
  - Figure 234. Block Diagram for Stm32F43Xxx765
  - Duration of the Processing766
  - Figure 235. Bit, Byte and Half-Word Swapping767
  - Message Digest Computing768
  - Message Padding769
  - Hash Operation770
  - Context Swapping771
  - Figure 236. HASH Interrupt Mapping Diagram773
  - HASH Control Register (HASH_CR) for Stm32F43Xxx776
  - HASH Data Input Register (HASH_DIN)779
  - HASH Start Register (HASH_STR)780
  - HASH Digest Registers (HASH_HR0..4/5/6/7)781
  - HASH Interrupt Enable Register (HASH_IMR)783
  - HASH Status Register (HASH_SR)784
  - HASH Context Swap Registers (Hash_Csrx)785
  - Table 116. HASH Register Map and Reset Values on Stm32F415/417Xx786
  - Table 117. HASH Register Map and Reset Values on Stm32F43Xxx787
  - Introduction789
- RTC Main Features790
- Figure 237. RTC Block Diagram791
- RTC Functional Description791
  - Real-Time Clock and Calendar792
  - Periodic Auto-Wakeup793
  - RTC Initialization and Configuration794
  - Reading the Calendar795
  - Resetting the RTC796
  - RTC Reference Clock Detection797
  - RTC Coarse Digital Calibration798
  - RTC Smooth Digital Calibration799
  - Timestamp Function801
  - Tamper Detection802
  - Calibration Clock Output803
  - Table 118. Effect of Low-Power Modes on RTC804
  - Alarm Output804
  - Table 119. Interrupt Control Bits805
- RTC Interrupts805
- RTC Registers806
  - RTC Date Register (RTC_DR)807
  - RTC Control Register (RTC_CR)808
  - RTC Initialization and Status Register (RTC_ISR)810
  - RTC Prescaler Register (RTC_PRER)813
  - RTC Calibration Register (RTC_CALIBR)814
  - RTC Alarm a Register (RTC_ALRMAR)815
  - RTC Alarm B Register (RTC_ALRMBR)816
  - RTC Write Protection Register (RTC_WPR)817
  - RTC Shift Control Register (RTC_SHIFTR)818
- RTC Time Stamp Date Register (RTC_TSDR)819
- RTC Timestamp Sub Second Register (RTC_TSSSR)820
- RTC Alarm a Sub Second Register (RTC_ALRMASSR)824
- RTC Alarm B Sub Second Register (RTC_ALRMBSSR)825
- Table 120. RTC Register Map and Reset Values826
- RTC Backup Registers (Rtc_Bkpxr)826
- Inter-Integrated Circuit (I 2 C) Interface829
- Mode Selection830
- Figure 238. I2C Bus Protocol831
- Figure 239. I2C Block Diagram for Stm32F40X/41X832
- Figure 240. I2C Block Diagram for Stm32F42X/43X833
- Figure 241. Transfer Sequence Diagram for Slave Transmitter835
- Figure 242. Transfer Sequence Diagram for Slave Receiver836
- Figure 243. Transfer Sequence Diagram for Master Transmitter839
- Figure 244. Transfer Sequence Diagram for Master Receiver841
- Error Conditions842
- Table 121. Maximum DNF[3:0] Value to be Compliant with Thd:dat(Max)843
- Programmable Noise Filter843
- SDA/SCL Line Control844
- Table 122. Smbus Vs. I2C845
- DMA Requests847
- Packet Error Checking848
- Table 123. I2C Interrupt Requests849
- Figure 245. I2C Interrupt Mapping Diagram850
- Table 124. I2C Register Map and Reset Values864
- SPI Introduction865
  - SPI Features866
  - Figure 246. SPI Block Diagram868
- SPI Functional Description868
  - Figure 247. Single Master/ Single Slave Application869
  - Configuring the SPI in Slave Mode871
  - Figure 248. Data Clock Timing Diagram871
  - Figure 249. TI Mode - Slave Mode, Single Transfer873
  - Figure 250. TI Mode - Slave Mode, Continuous Transfer873
  - Configuring the SPI in Master Mode874
  - Figure 251. TI Mode - Master Mode, Single Transfer875
  - Figure 252. TI Mode - Master Mode, Continuous Transfer875
  - Configuring the SPI for Half-Duplex Communication876
  - Figure 253. TXE/RXNE/BSY Behavior in Master / Full-Duplex Mode (BIDIMODE=0 and RXONLY=0) in the Case of Continuous Transfers879
  - Figure 254. TXE/RXNE/BSY Behavior in Slave / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the Case of Continuous Transfers879
  - Case of Continuous Transfers880
  - Figure 255. TXE/BSY Behavior in Master Transmit-Only Mode (BIDIMODE=0 and RXONLY=0) in880
  - Continuous Transfers881
  - Figure 256. TXE/BSY in Slave Transmit-Only Mode (BIDIMODE=0 and RXONLY=0) in the Case of881
  - Figure 257. RXNE Behavior in Receive-Only Mode (BIDIRMODE=0 and RXONLY=1)882
  - In the Case of Continuous Transfers882
  - CRC Calculation883
  - Figure 258. TXE/BSY Behavior When Transmitting (BIDIRMODE=0 and RXONLY=0)883
  - In the Case of Discontinuous Transfers883
  - Status Flags885
  - Disabling the SPI886
  - SPI Communication Using DMA (Direct Memory Addressing)887
  - Figure 259. Transmission Using DMA888
  - Figure 260. Reception Using DMA888
  - Error Flags889
  - Figure 261. TI Mode Frame Format Error Detection890
  - SPI Interrupts890
  - Table 125. SPI Interrupt Requests890
  - Figure 262. I 2 S Block Diagram891
  - Figure 263. I2S Full Duplex Block Diagram892
  - Supported Audio Protocols893
  - Figure 264. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, CPOL = 0)894
  - Figure 265. I 2 S Philips Standard Waveforms (24-Bit Frame with CPOL = 0)894
  - Figure 266. Transmitting 0X8Eaa33895
  - Figure 267. Receiving 0X8Eaa33895
  - Figure 268. I895
  - Figure 269. Example896
  - Figure 270. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length with CPOL = 0896
  - Figure 271. MSB Justified 24-Bit Frame Length with CPOL = 0897
  - Figure 272. MSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0897
  - Figure 273. LSB Justified 16-Bit or 32-Bit Full-Accuracy with CPOL = 0897
  - Figure 274. LSB Justified 24-Bit Frame Length with CPOL = 0898
  - Figure 275. Operations Required to Transmit 0X3478Ae898
  - Figure 276. Operations Required to Receive 0X3478Ae898
  - Figure 277. LSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0899
  - Figure 278. Example of LSB Justified 16-Bit Extended to 32-Bit Packet Frame899
  - Figure 279. PCM Standard Waveforms (16-Bit)900
  - Figure 280. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)900
  - Clock Generator901
  - Figure 281. Audio Sampling Frequency Definition901
  - Figure 282. I901
  - Table 126. Audio Frequency Precision (for PLLM VCO = 1 Mhz or 2 Mhz)902
  - Status Flags906
- Error Flags907
  - DMA Features908
  - Table 127. I908
  - SPI Control Register 2 (SPI_CR2)911
  - SPI Status Register (SPI_SR)912
  - SPI Data Register (SPI_DR)913
  - Table 128. SPI Register Map and Reset Values918
Serial Audio Interface (SAI)919
- Main Features920
- Figure 283. Functional Block Diagram921
- Main SAI Modes922
- Figure 284. Audio Frame923
- SAI Synchronization Mode923
- Slot Configuration926
- Figure 287. Slot Size Configuration with FBOFF = 0 in Sai_Xslotr927
- Figure 288. First Bit Offset927
- Figure 289. Audio Block Clock Generator Overview928
- SAI Clock Generator928
- Table 129. Example of Possible Audio Frequency Sampling Range929
- Internal Fifos929
- Figure 290. AC'97 Audio Frame932
- AC'97 Link Controller932
- Specific Features933
- SAI DMA Interface942
- SAI Registers943
Transmitter (USART)958
- USART Functional Description959
  - Figure 296. USART Block Diagram961
  - Figure 297. Word Length Programming962
  - USART Character Description962
  - Transmitter963
  - Figure 298. Configurable Stop Bits964
  - Figure 299. TC/TXE Behavior When Transmitting965
  - Figure 300. Start Bit Detection When Oversampling by 16 or 8966
  - Receiver966
  - Figure 301. Data Sampling When Oversampling by 16969
  - Figure 302. Data Sampling When Oversampling by 8970
  - Table 132. Noise Detection from Sampled Data970
  - Fractional Baud Rate Generation971
  - Oversampling by 16973
  - Table 133. Error Calculation for Programmed Baud Rates at F973
- PCLK = 8 Mhz or F PCLK = 12 Mhz973
  - Oversampling by 8974
  - Oversampling by 16974
- PCLK = 16 Mhz or F PCLK = 24 Mhz974
  - Oversampling by 8975
  - Oversampling by 16976
  - Oversampling by 8976
  - Oversampling by 16977
  - Oversampling by 8978
  - Oversampling by 16979
  - Oversampling by 8980
  - USART Receiver Tolerance to Clock Deviation981
  - Table 143. USART Receiver's Tolerance When DIV Fraction Is 0982
  - Table 144. USART Receiver Tolerance When Div_Fraction Is Different from 0982
  - Multiprocessor Communication982
  - Figure 303. Mute Mode Using Idle Line Detection983
  - Table 145. Frame Formats984
  - Figure 304. Mute Mode Using Address Mark Detection984
  - Parity Control984
  - LIN (Local Interconnection Network) Mode985
  - Figure 305. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)986
  - Figure 306. Break Detection in LIN Mode Vs. Framing Error Detection987
  - USART Synchronous Mode987
  - Figure 307. USART Example of Synchronous Transmission988
  - Figure 308. USART Data Clock Timing Diagram (M=0)988
  - Figure 309. USART Data Clock Timing Diagram (M=1)989
  - Figure 310. RX Data Setup/Hold Time989
  - Single-Wire Half-Duplex Communication989
  - Figure 311. ISO 7816-3 Asynchronous Protocol990
  - Smartcard990
  - Figure 312. Parity Error Detection Using the 1.5 Stop Bits991
  - Irda SIR ENDEC Block992
  - Figure 313. Irda SIR ENDEC- Block Diagram993
  - Figure 314. Irda Data Modulation (3/16) -Normal Mode993
  - Continuous Communication Using DMA994
  - Figure 315. Transmission Using DMA995
  - Figure 316. Reception Using DMA996
  - Figure 317. Hardware Flow Control between 2 Usarts996
  - Figure 318. RTS Flow Control997
  - Figure 319. CTS Flow Control997
  - Table 146. USART Interrupt Requests998
  - Figure 320. USART Interrupt Mapping Diagram998
- USART Interrupts998
  - Table 147. USART Mode Configuration999
  - Data Register (USART_DR)1002
  - Control Register 2 (USART_CR2)1005
  - Control Register 3 (USART_CR3)1006
  - Guard Time and Prescaler Register (USART_GTPR)1009
  - Table 148. USART Register Map and Reset Values1010
- SDIO Main Features1011
- Figure 321. SDIO "No Response" and "No Data" Operations1012
- Figure 322. SDIO (Multiple) Block Read Operation1012
- Figure 323. SDIO (Multiple) Block Write Operation1013
- Figure 324. SDIO Sequential Read Operation1013
- Figure 325. SDIO Sequential Write Operation1013
- Figure 326. SDIO Block Diagram1014
- SDIO Functional Description1014
  - Figure 327. SDIO Adapter1015
  - Table 149. SDIO I/O Definitions1015
  - Figure 328. Control Unit1016
  - Figure 329. SDIO Adapter Command Path1017
  - Figure 330. Command Path State Machine (CPSM)1018
  - Figure 331. SDIO Command Transfer1019
  - Table 150. Command Format1019
  - Table 151. Short Response Format1020
  - Table 152. Long Response Format1020
  - Table 153. Command Path Status Flags1020
  - Figure 332. Data Path1021
  - Figure 333. Data Path State Machine (DPSM)1022
  - Table 154. Data Token Format1023
  - Table 155. Transmit FIFO Status Flags1024
  - SDIO APB2 Interface1025
  - Table 156. Receive FIFO Status Flags1025
- Card Functional Description1026
  - Card Identification Process1027
  - Block Write1028
  - Block Read1029
  - Erase: Group Erase and Sector Erase1031
  - Card Status Register1034
  - Table 157. Card Status1035
  - SD Status Register1037
  - Table 158. SD Status1038
  - Table 159. Speed Class Code Field1039
  - Table 160. Performance Move Field1039
  - Table 161. AU_SIZE Field1040
  - Table 162. Maximum au Size1040
  - Table 163. Erase Size Field1040
  - Table 164. Erase Timeout Field1041
  - Table 165. Erase Offset Field1041
  - SD I/O Mode1041
  - Commands and Responses1042
  - Table 166. Block-Oriented Write Commands1043
  - Table 167. Block-Oriented Write Protection Commands1044
  - Table 168. Erase Commands1044
  - Table 169. I/O Mode Commands1045
  - Table 170. Lock Card1045
  - Table 171. Application-Specific Commands1045
  - Table 172. R1 Response1046
- Response Formats1046
  - R3 (OCR Register)1047
  - Table 173. R2 Response1047
  - Table 174. R3 Response1047
  - Table 175. R4 Response1047
  - R5 (Interrupt Request)1048
  - Table 176. R4B Response1048
  - Table 177. R5 Response1048
  - Table 178. R6 Response1049
- SDIO I/O Card-Specific Operations1049
  - SDIO I/O Read Wait Operation by SDIO_D2 Signaling1050
- CE-ATA Specific Operations1051
- HW Flow Control1052
  - SDI Clock Control Register (SDIO_CLKCR)1053
  - SDIO Argument Register (SDIO_ARG)1054
  - SDIO Command Register (SDIO_CMD)1055
  - Table 179. Response Type and Sdio_Respx Registers1056
  - SDIO Command Response Register (SDIO_RESPCMD)1056
  - SDIO Data Timer Register (SDIO_DTIMER)1057
  - SDIO Data Control Register (SDIO_DCTRL)1058
  - SDIO Data Counter Register (SDIO_DCOUNT)1059
  - SDIO Status Register (SDIO_STA)1060
  - SDIO Interrupt Clear Register (SDIO_ICR)1061
  - SDIO Mask Register (SDIO_MASK)1063
  - SDIO FIFO Counter Register (SDIO_FIFOCNT)1065
  - Table 180. SDIO Register Map1066
  - SDIO Data FIFO Register (SDIO_FIFO)1066
- Bxcan Introduction1068
- Figure 334. CAN Network Topology1069
- Bxcan General Description1069
  - Control, Status and Configuration Registers1070
  - Figure 335. Dual CAN Block Diagram1071
- Bxcan Operating Modes1071
  - Initialization Mode1072
  - Figure 336. Bxcan Operating Modes1073
- Test Mode1073
- Figure 337. Bxcan in Silent Mode1074
- Figure 338. Bxcan in Loop Back Mode1074
- Figure 339. Bxcan in Combined Mode1075
- Debug Mode1075
  - Figure 340. Transmit Mailbox States1076
  - Figure 341. Receive FIFO States1077
  - Time Triggered Communication Mode1077
  - Identifier Filtering1078
  - Figure 342. Filter Bank Scale Configuration - Register Organization1080
  - Figure 343. Example of Filter Numbering1081
  - Figure 344. Filtering Mechanism - Example1082
  - Message Storage1082
  - Figure 345. CAN Error State Diagram1083
  - Table 181. Transmit Mailbox Mapping1083
  - Table 182. Receive Mailbox Mapping1083
  - Error Management1084
  - Figure 346. Bit Timing1085
  - Figure 347. CAN Frames1086
- Bxcan Interrupts1086
- Figure 348. Event Flags and Interrupt Generation1087
- CAN Registers1088
  - CAN Mailbox Registers1098
  - Figure 349. RX and TX Mailboxes1098
  - CAN Filter Registers1105
  - Table 183. Bxcan Register Map and Reset Values1109
DMA Controller1113
- Ethernet Introduction1113
- Ethernet Pins1116
- Figure 350. ETH Block Diagram1117
- Ethernet Functional Description: SMI, MII and RMII1117
- Ethernet Functional Description: MAC 802.31125
- Ethernet Functional Description: DMA Controller Operation1155
- Ethernet Interrupts1182
- Ethernet Register Descriptions1183
- OTG_FS Introduction1233
- OTG Dual Role Device (DRD)1237
- SOF Trigger1247
  - Peripheral Sofs1248
  - Figure 391. Updating OTG_FS_HFIR Dynamically1249
- Dynamic Update of the OTG_FS_HFIR Register1249
- Figure 392. Device-Mode FIFO Address Mapping and AHB FIFO Access Mapping1250
- USB Data Fifos1250
- OTG_FS Interrupts1254
- Figure 394. Interrupt Hierarchy1255
- OTG_FS Control and Status Registers1255
- OTG_FS Programming Model1324
USB On-The-Go High-Speed (OTG_HS)1369
- General Features1370
- Host-Mode Features1371
- Figure 410. USB OTG Interface Block Diagram1372
- High-Speed OTG PHY1372
- OTG Dual-Role Device1373
- USB Functional Description in Peripheral Mode1374
- Peripheral Endpoints1375
- USB Functional Description on Host Mode1378
- USB_HS Power Modes1384
- FIFO RAM Allocation1385
- Figure 411. Updating OTG_HS_HFIR Dynamically1385
- OTG_HS Interrupts1386
- Figure 412. Interrupt Hierarchy1387
- OTG_HS Control and Status Registers1387
- CSR Memory Map1388
- OTG_HS Programming Model1473
Flexible Static Memory Controller (FSMC)1530
- Figure 432. FSMC Block Diagram1531
- Supported Memories and Transactions1532
- Table 211. NOR/PSRAM Bank Selection1533
- Figure 433. FSMC Memory Banks1533
- External Device Address Mapping1533
  - NAND/PC Card Address Mapping1534
  - Table 212. External Memory Address1534
  - Table 213. Memory Mapping and Timing Registers1534
  - Table 214. NAND Bank Selections1535
- NOR Flash/Psram Controller1535
  - External Memory Interface Signals1536
  - Table 215. Programmable NOR/PSRAM Access Parameters1536
  - Table 216. Nonmultiplexed I/O nor Flash1536
  - Table 217. Multiplexed I/O nor Flash1537
  - Table 218. Nonmultiplexed I/Os PSRAM/SRAM1537
  - Table 219. Multiplexed I/O PSRAM1537
  - And Transactions1538
  - Supported Memories and Transactions1538
  - Table 220. nor Flash/Psram Controller: Example of Supported Memories1538
  - General Timing Rules1539
  - Figure 434. Mode1 Read Accesses1540
  - NOR Flash/Psram Controller Asynchronous Transactions1540
  - Figure 435. Mode1 Write Accesses1541
  - Table 221. Fsmc_Bcrx Bit Fields1541
  - Table 222. Fsmc_Btrx Bit Fields1542
  - Figure 436. Modea Read Accesses1543
  - Figure 437. Modea Write Accesses1543
  - Table 223. Fsmc_Bcrx Bit Fields1544
  - Table 224. Fsmc_Btrx Bit Fields1544
  - Figure 438. Mode2 and Mode B Read Accesses1545
  - Table 225. Fsmc_Bwtrx Bit Fields1545
  - Figure 439. Mode2 Write Accesses1546
  - Figure 440. Mode B Write Accesses1546
  - Table 226. Fsmc_Bcrx Bit Fields1547
  - Table 227. Fsmc_Btrx Bit Fields1547
  - Figure 441. Mode C Read Accesses1548
  - Table 228. Fsmc_Bwtrx Bit Fields1548
  - Figure 442. Mode C Write Accesses1549
  - Table 229. Fsmc_Bcrx Bit Fields1549
  - Table 230. Fsmc_Btrx Bit Fields1550
  - Table 231. Fsmc_Bwtrx Bit Fields1550
  - Figure 443. Mode D Read Accesses1551
  - Figure 444. Mode D Write Accesses1551
  - Table 232. Fsmc_Bcrx Bit Fields1552
  - Table 233. Fsmc_Btrx Bit Fields1552
  - Figure 445. Multiplexed Read Accesses1553
  - Table 234. Fsmc_Bwtrx Bit Fields1553
  - Figure 446. Multiplexed Write Accesses1554
  - Table 235. Fsmc_Bcrx Bit Fields1554
  - Table 236. Fsmc_Btrx Bit Fields1555
  - Figure 447. Asynchronous Wait During a Read Access1556
  - Figure 448. Asynchronous Wait During a Write Access1557
  - Synchronous Transactions1558
  - Figure 449. Wait Configurations1559
  - Figure 450. Synchronous Multiplexed Read Mode - NOR, PSRAM (CRAM)1560
  - Table 237. Fsmc_Bcrx Bit Fields1560
  - Table 238. Fsmc_Btrx Bit Fields1561
  - Figure 451. Synchronous Multiplexed Write Mode - PSRAM (CRAM)1562
  - Table 239. Fsmc_Bcrx Bit Fields1562
  - Table 240. Fsmc_Btrx Bit Fields1563
  - NOR/PSRAM Control Registers1564
- NAND Flash/Pc Card Controller1571
  - External Memory Interface Signals1572
  - Table 241. Programmable NAND/PC Card Access Parameters1572
  - Table 242. 8-Bit NAND Flash1572
  - Table 243. 16-Bit NAND Flash1573
  - Table 244. 16-Bit PC Card1573
  - NAND Flash / PC Card Supported Memories and Transactions1574
  - Table 245. Supported Memories and Transactions1574
  - Figure 452. NAND/PC Card Controller Timing for Common Memory Access1575
  - NAND Flash Operations1575
  - Figure 453. Access to Non 'CE Don't Care' NAND-Flash1576
  - NAND Flash Pre-Wait Functionality1576
    - In NAND Flash Memory1577
  - PC Card/Compactflash Operations1578
  - Table 246. 16-Bit PC-Card Signals and Access Type1579
  - NAND Flash/Pc Card Control Registers1580
  - Table 247. ECC Result Relevant Bits1586
  - Table 248. FSMC Register Map1587
- FMC Main Features1589
- Block Diagram1590
- Figure 454. FMC Block Diagram1591
- AHB Interface1591
  - Supported Memories and Transactions1592
- External Device Address Mapping1593
  - Figure 455. FMC Memory Banks1594
  - NOR/PSRAM Address Mapping1594
  - Table 249. NOR/PSRAM Bank Selection1594
  - NAND Flash Memory/Pc Card Address Mapping1595
  - Table 250. NOR/PSRAM External Memory Address1595
  - Table 251. NAND/PC Card Memory Mapping and Timing Registers1595
  - Table 252. NAND Bank Selection1596
  - Table 253. SDRAM Bank Selection1596
  - Table 254. SDRAM Address Mapping1596
  - Table 255. SDRAM Address Mapping with 8-Bit Data Bus Width1597
  - Table 256. SDRAM Address Mapping with 16-Bit Data Bus Width1598
  - Table 257. SDRAM Address Mapping with 32-Bit Data Bus Width1598
- NOR Flash/Psram Controller1599
  - External Memory Interface Signals1600
  - Table 258. Programmable NOR/PSRAM Access Parameters1600
  - Table 259. Non-Multiplexed I/O nor Flash Memory1601
  - Table 260. 16-Bit Multiplexed I/O nor Flash Memory1601
  - Table 261. Non-Multiplexed I/Os PSRAM/SRAM1601
  - Supported Memories and Transactions1602
  - Table 262. 16-Bit Multiplexed I/O PSRAM1602
  - Table 263. nor Flash/Psram: Example of Supported Memories and Transactions1603
  - General Timing Rules1604
  - Figure 456. Mode1 Read Access Waveforms1605
  - Figure 457. Mode1 Write Access Waveforms1605
  - Table 264. Fmc_Bcrx Bit Fields1606
  - Table 265. Fmc_Btrx Bit Fields1606
  - Figure 458. Modea Read Access Waveforms1607
  - Figure 459. Modea Write Access Waveforms1608
  - Table 266. Fmc_Bcrx Bit Fields1608
  - Table 267. Fmc_Btrx Bit Fields1609
  - Table 268. Fmc_Bwtrx Bit Fields1609
  - Figure 460. Mode2 and Mode B Read Access Waveforms1610
  - Figure 461. Mode2 Write Access Waveforms1610
  - Figure 462. Modeb Write Access Waveforms1611
  - Table 269. Fmc_Bcrx Bit Fields1611
  - Table 270. Fmc_Btrx Bit Fields1612
  - Table 271. Fmc_Bwtrx Bit Fields1612
  - Figure 463. Modec Read Access Waveforms1613
  - Figure 464. Modec Write Access Waveforms1613
  - Table 272. Fmc_Bcrx Bit Fields1614
  - Table 273. Fmc_Btrx Bit Fields1614
  - Figure 465. Moded Read Access Waveforms1615
  - Table 274. Fmc_Bwtrx Bit Fields1615
  - Figure 466. Moded Write Access Waveforms1616
  - Table 275. Fmc_Bcrx Bit Fields1616
  - Table 276. Fmc_Btrx Bit Fields1617
  - Table 277. Fmc_Bwtrx Bit Fields1617
  - Figure 467. Muxed Read Access Waveforms1618
  - Figure 468. Muxed Write Access Waveforms1618
  - Table 278. Fmc_Bcrx Bit Fields1619
  - Table 279. Fmc_Btrx Bit Fields1619
  - Figure 469. Asynchronous Wait During a Read Access Waveforms1620
  - Figure 470. Asynchronous Wait During a Write Access Waveforms1621
  - Synchronous Transactions1621
  - Figure 471. Wait Configuration Waveforms1623
  - Figure 472. Synchronous Multiplexed Read Mode Waveforms - NOR, PSRAM (CRAM)1623
  - Table 280. Fmc_Bcrx Bit Fields1624
  - Table 281. Fmc_Btrx Bit Fields1624
  - Figure 473. Synchronous Multiplexed Write Mode Waveforms - PSRAM (CRAM)1625
  - Table 282. Fmc_Bcrx Bit Fields1625
  - Table 283. Fmc_Btrx Bit Fields1626
  - NOR/PSRAM Controller Registers1627
  - NAND Flash/Pc Card Controller1634
  - External Memory Interface Signals1635
  - Table 284. Programmable NAND Flash/Pc Card Access Parameters1635
  - Table 285. 8-Bit NAND Flash1635
  - Table 286. 16-Bit NAND Flash1636
  - Table 287. 16-Bit PC Card1636
  - NAND Flash / PC Card Supported Memories and Transactions1637
  - Table 288. Supported Memories and Transactions1637
  - Figure 474. NAND Flash/Pc Card Controller Waveforms for Common Memory Access1638
  - NAND Flash Operations1638
  - Figure 475. Access to Non 'CE Don't Care' NAND-Flash1639
  - NAND Flash Prewait Functionality1639
  - In NAND Flash Memory1640
    - PC Card/Compactflash Operations1641
    - Table 289. 16-Bit PC-Card Signals and Access Type1641
    - NAND Flash/Pc Card Controller Registers1642
  - Table 290. ECC Result Relevant Bits1649
  - Table 291. SDRAM Signals1650
- SDRAM Controller1650
  - SDRAM Controller Functional Description1651
  - Figure 476. Burst Write SDRAM Access Waveforms1652
  - Figure 477. Burst Read SDRAM Access1653
  - Figure 478. Logic Diagram of Read Access with RBURST Bit Set (CAS=2, RPIPE=0)1654
  - Figure 479. Read Access Crossing Row Boundary1656
  - Figure 480. Write Access Crossing Row Boundary1656
  - Low Power Modes1657
  - Figure 481. Self-Refresh Mode1659
  - Figure 482. Power-Down Mode1660
  - SDRAM Controller Registers1661
  - Table 292. FMC Register Map1667
  - Figure 483. Block Diagram of STM32 MCU and Cortex ® -M4 with FPU-Level1670
  - Debug Support1670
- Overview1670
- SWJ Debug Port (Serial Wire and JTAG)1671
  - Figure 484. SWJ Debug Port1672
  - Mechanism to Select the JTAG-DP or the SW-DP1672
  - Table 293. SWJ Debug Port Pins1673
  - Table 294. Flexible SWJ-DP Pin Assignment1673
  - Internal Pull-Up and Pull-Down on JTAG Pins1674
  - Using Serial Wire and Releasing the Unused Debug Pins as Gpios1675
  - Figure 485. JTAG TAP Connections1676
- ID Codes and Locking Mechanism1677
  - Boundary Scan TAP1678
  - Table 295. JTAG Debug Port Data Registers1678
  - Table 296. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]1679
  - Table 297. Packet Request (8-Bits)1680
- SW Debug Port1680
  - SW-DP State Machine (Reset, Idle States, ID Code)1681
  - Table 298. ACK Response (3 Bits)1681
  - Table 299. DATA Transfer (33 Bits)1681
  - DP and AP Read/Write Accesses1682
  - Table 300. SW-DP Registers1682
  - SW-AP Registers1683
  - Table 301. Cortex1684
  - Table 302. Core Debug Registers1685
- Capability of the Debugger Host to Connect under System Reset1686
- DWT (Data Watchpoint Trigger)1687
- Table 303. Main ITM Registers1688
- Table 304. Main ETM Registers1689
- ETM (Embedded Trace Macrocell)1689
  - Configuration Example1690
  - Debug MCU Configuration Register1691
  - Debug MCU APB1 Freeze Register (DBGMCU_APB1_FZ)1692
  - Debug MCU APB2 Freeze Register (DBGMCU_APB2_FZ)1694
  - Figure 486. TPIU Block Diagram1695
- TPIU (Trace Port Interface Unit)1695
  - Table 305. Asynchronous TRACE Pin Assignment1696
  - Table 306. Synchronous TRACE Pin Assignment1696
  - Table 307. Flexible TRACE Pin Assignment1697
  - TPUI Formatter1697
  - TPUI Frame Synchronization Packets1698
  - Asynchronous Mode1699
  - Table 308. Important TPIU Registers1699
  - Example of Configuration1700
  - Table 309. DBG Register Map and Reset Values1700
Device Electronic Signature1702
- Flash Size1703
- Table 310. Document Revision History1704

Brand	STMicroelectronics
Model	STM32F405
Category	Controller
Language	English

STMicroelectronics STM32F405 User Manual

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STMicroelectronics STM32F405 Specifications

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