DocID018909 Rev 11 825/1731
RM0090 Real-time clock (RTC)
828
Note: This register can be written only when ALRAE is reset in RTC_CR register, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 794
26.6.19 RTC alarm B sub second register (RTC_ALRMBSSR)
Address offset: 0x48
Backup domain reset value: 0x0000 0000
System reset: not affected
Note: This register can be written only when ALRBIE is reset in RTC_CR register, or in
initialization mode.
This register is write protected.The write access procedure is described in Section : RTC
register write protection
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved MASKSS[3:0] Reserved
rrrrrwrwrwrwrrrrrrrr
15141312111098765432 1 0
Reserved SS[14:0]
r rwrwrw rwrwrwrwrwrwrwrwrww rw rw
Bits 31:28 Reserved
Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit
0x0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is
incremented (assuming that the rest of the fields match).
0x1: SS[14:1] are don’t care in Alarm B comparison. Only SS[0] is compared.
0x2: SS[14:2] are don’t care in Alarm B comparison. Only SS[1:0] are compared.
0x3: SS[14:3] are don’t care in Alarm B comparison. Only SS[2:0] are compared.
...
0xC: SS[14:12] are don’t care in Alarm B comparison. SS[11:0] are compared.
0xD: SS[14:13] are don’t care in Alarm B comparison. SS[12:0] are compared.
0xE: SS[14] is don’t care in Alarm B comparison. SS[13:0] are compared.
0xF: All 15 SS bits are compared and must match to activate alarm.
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be
different from 0 only after a shift operation.
Bits 23:15 Reserved
Bits 14:0 SS[14:0]: Sub seconds value
This value is compared with the contents of the synchronous prescaler’s counter to
determine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.
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