Flexible memory controller (FMC) RM0090
1602/1731 DocID018909 Rev 11
The maximum capacity is 512 Mbits.
PSRAM, 16-bit multiplexed I/Os
The maximum capacity is 512 Mbits (26 address lines).
37.5.2 Supported memories and transactions
Table 263 below shows an example of the supported devices, access modes and
transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and
SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in
this example.
NE[x] O
Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e.
CRAM))
NOE O Output enable
NWE O Write enable
NL(= NADV) O Address valid only for PSRAM input (memory signal name: NADV)
NWAIT I PSRAM wait input signal to the FMC
NBL[3] O Byte3 Upper byte enable (memory signal name: NUB)
NBL[2] O Byte2 Lowed byte enable (memory signal name: NLB)
NBL[1] O Byte1 Upper byte enable (memory signal name: NLB)
NBL[0] O Byte0 Lower byte enable (memory signal name: NLB)
Table 262. 16-Bit multiplexed I/O PSRAM
FMC signal name I/O Function
CLK O Clock (for synchronous access)
A[25:16] O Address bus
AD[15:0] I/O
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
A[15:0] and data D[15:0] are multiplexed on the databus)
NE[x] O
Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e.
CRAM))
NOE O Output enable
NWE O Write enable
NL(= NADV) O Address valid PSRAM input (memory signal name: NADV)
NWAIT I PSRAM wait input signal to the FMC
NBL[1] O Upper byte enable (memory signal name: NUB)
NBL[0] O Lowed byte enable (memory signal name: NLB)
Table 261. Non-multiplexed I/Os PSRAM/SRAM (continued)
FMC signal name I/O Function
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