Universal synchronous asynchronous receiver transmitter (USART) RM0090
976/1731 DocID018909 Rev 11
Table 137. Error calculation for programmed baud rates at f
PCLK
= 8 MHz or f
PCLK
= 16 MHz,
oversampling by 16
(1)
Oversampling by 16 (OVER8=0)
Baud rate f
PCLK
= 8 MHz f
PCLK
= 16 MHz
S.No Desired Actual
Value
programme
d in the
baud rate
register
% Error =
(Calculated -
Desired)B.Rate
/Desired B.Rate
Actual
Value
programmed
in the baud
rate register
% Error
1. 2.4 KBps 2.400 KBps 208.3125 0.00% 2.400 KBps 416.6875 0.00%
2. 9.6 KBps 9.604 KBps 52.0625 0.04% 9.598 KBps 104.1875 0.02%
3. 19.2 KBps 19.185 KBps 26.0625 0.08% 19.208 KBps 52.0625 0.04%
4. 57.6 KBps 57.554 KBps 8.6875 0.08% 57.554 KBps 17.3750 0.08%
5. 115.2 KBps 115.942 KBps 4.3125 0.64% 115.108 KBps 8.6875 0.08%
6. 230.4 KBps
228.571
KBps
2.1875 0.79% 231.884 KBps 4.3125 0.64%
7. 460.8 KBps
470.588
KBps
1.0625 2.12% 457.143 KBps 2.1875 0.79%
8. 896 KBps NA NA NA 888.889 KBps 1.1250 0.79%
9. 921.6 KBps NA NA NA 941.176 KBps 1.0625 2.12%
10. 1.792 MBps NA NA NA NA NA NA
11. 1.8432 MBps NA NA NA NA NA NA
12. 3.584 MBps NA NA NA NA NA NA
13. 3.6864 MBps NA NA NA NA NA NA
14. 7.168 MBps NA NA NA NA NA NA
15. 7.3728 MBps NA NA NA NA NA NA
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
Table 138. Error calculation for programmed baud rates at f
PCLK
= 8 MHz or f
PCLK
= 16 MHz,
oversampling by 8
(1)
Oversampling by 8 (OVER8=1)
Baud rate f
PCLK
= 8 MHz f
PCLK
= 16 MHz
S.No Desired Actual
Value
programmed
in the baud
rate register
% Error =
(Calculated -
Desired)B.Rate
/Desired B.Rate
Actual
Value
programmed
in the baud
rate register
%
Error
1. 2.4 KBps 2.400 KBps 416.625 0.01% 2.400 KBps 833.375 0.00%
2. 9.6 KBps 9.604 KBps 104.125 0.04% 9.598 KBps 208.375 0.02%
3. 19.2 KBps 19.185 KBps 52.125 0.08% 19.208 KBps 104.125 0.04%
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