Universal synchronous asynchronous receiver transmitter (USART) RM0090
980/1731 DocID018909 Rev 11
11 1.792 MBps 1.826 MBps 1.4375 1.9 1.787 MBps 2.9375 0.27
12
1.8432
MBps
1.826 MBps 1.4375 0.93 1.826 MBps 2.875 0.93
13 3.584 MBps N.A N.A N.A 3.652 MBps 1.4375 1.9
14
3.6864
MBps
N.A N.A N.A 3.652 MBps 1.4375 0.93
15 7.168 MBps N.A N.A N.A N.A N.A N.A
16
7.3728
MBps
N.A N.A N.A N.A N.A N.A
18 9 MBps N.A N.A N.A N.A N.A N.A
20 10.5 MBps N.A N.A N.A N.A N.A N.A
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
2. Only USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device
datasheets for the maximum values for PCLK1 and PCLK2.
Table 141. Error calculation for programmed baud rates at f
PCLK
= 42 MHz or f
PCLK
= 84 Hz,
oversampling by 16
(1)(2)
(continued)
Oversampling by 16 (OVER8=0)
Baud rate f
PCLK
= 42 MHz f
PCLK
= 84 MHz
S.No Desired Actual
Value
programme
d in the
baud rate
register
% Error =
(Calculated -
Desired)B.Rate
/Desired B.Rate
Actual
Value
programmed
in the baud
rate register
%
Error
Table 142. Error calculation for programmed baud rates at f
PCLK
= 42 MHz or f
PCLK
= 84 MHz,
oversampling by 8
(1)(2)
Oversampling by 8 (OVER8=1)
Baud rate f
PCLK
= 42 MHz f
PCLK
= 84 MHz
S.No Desired Actual
Value
programme
d in the
baud rate
register
% Error =
(Calculated -
Desired)B.Rate
/Desired B.Rate
Actual
Value
programmed
in the baud
rate register
%
Error
1. 1.2 KBps 1.2 KBps 4375 0 1.2 KBps 8750 0
2. 2.4 KBps 2.4 KBps 2187.5 0 2.4 KBps 4375 0
3. 9.6 KBps 9.6 KBps 546.875 0 9.6 KBps 1093.75 0
4. 19.2 KBps 19.195 KBps 273.5 0.02 19.2 KBps 546.875 0
5. 38.4 KBps 38.391 KBps 136.75 0.02 38.391 KBps 273.5 0.02
6. 57.6 KBps 57.613 KBps 91.125 0.02 57.613 KBps 182.25 0.02
7. 115.2 KBps 115.068 KBps 45.625 0.11 115.226 KBps 91.125 0.02
8. 230.4 KBps 230.769 KBps 22.75 0.11 230.137 KBps 45.625 0.11
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