STMicroelectronics STM32F405 User Manual

DocID018909 Rev 11 1389/1731
RM0090 USB on-the-go high-speed (OTG_HS)
1529
Figure 413. CSR memory map
1. x = 5 in peripheral mode and x = 11 in host mode.
Global CSR map
These registers are available in both host and peripheral modes.
0000h
Core global CSRs (1 Kbyte)
0400h
Host mode CSRs (1 Kbyte)
0800h
Device mode CSRs (1.5 Kbyte)
0E00h
Power and clock gating CSRs (0.5 Kbyte)
1000h
Device EP 0/Host channel 0 FIFO (4 Kbyte)
2000h
Device EP1/Host channel 1 FIFO (4 Kbyte)
3000h
Device EP (x – 1)
(1)
/Host channel (x – 1)
(1)
FIFO (4 Kbyte)
Device EP x
(1)
/Host channel x
(1)
FIFO (4 Kbyte)
Reserved
DFIFO
push/pop
to this region
2 0000h
3 FFFFh
Direct access to data FIFO RAM
for debugging (128 Kbyte)
DFIFO
debug read/
write to this
region
ai15615b
Table 203. Core global control and status registers (CSRs)
Acronym
Address
offset
Register name
OTG_HS_GOTGCTL 0x000 OTG_HS control and status register (OTG_HS_GOTGCTL) on page 1393
OTG_HS_GOTGINT 0x004 OTG_HS interrupt register (OTG_HS_GOTGINT) on page 1395
OTG_HS_GAHBCFG 0x008 OTG_HS AHB configuration register (OTG_HS_GAHBCFG) on page 1397
OTG_HS_GUSBCFG 0x00C OTG_HS USB configuration register (OTG_HS_GUSBCFG) on page 1398
OTG_HS_GRSTCTL 0x010 OTG_HS reset register (OTG_HS_GRSTCTL) on page 1401
OTG_HS_GINTSTS 0x014 OTG_HS core interrupt register (OTG_HS_GINTSTS) on page 1404
OTG_HS_GINTMSK 0x018 OTG_HS interrupt mask register (OTG_HS_GINTMSK) on page 1408

STMicroelectronics STM32F405 Specifications

General

Brand	STMicroelectronics
Model	STM32F405
Category	Controller
Language	English