Flexible memory controller (FMC) RM0090
1624/1731 DocID018909 Rev 11
they are held low.
Table 280. FMC_BCRx bit fields
Bit No. Bit name Value to set
31-21 Reserved 0x000
20 CCLKEN As needed
19 CBURSTRW No effect on synchronous read
18-16 CPSIZE As needed (0x1 for CRAM 1.5)
15 ASYNCWAIT 0x0
14 EXTMOD 0x0
13 WAITEN
to be set to 1 if the memory supports this feature, to be kept at 0
otherwise
12 WREN no effect on synchronous read
11 WAITCFG to be set according to memory
10 WRAPMOD 0x0
9 WAITPOL to be set according to memory
8 BURSTEN 0x1
7 Reserved 0x1
6 FACCEN Set according to memory support (NOR Flash memory)
5-4 MWID As needed
3-2 MTYP[1:0] 0x1 or 0x2
1 MUXEN As needed
0 MBKEN 0x1
Table 281. FMC_BTRx bit fields
Bit No. Bit name Value to set
31:30 Reserved 0x0
29:28 ACCMOD 0x0
27-24 DATLAT Data latency
27-24 DATLAT Data latency
23-20 CLKDIV
0x0 to get CLK = HCLK (Not supported)
0x1 to get CLK = 2 × HCLK
..
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST Don’t care
7-4 ADDHLD Don’t care
3-0 ADDSET[3:0] Don’t care
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