Flexible memory controller (FMC) RM0090
1620/1731 DocID018909 Rev 11
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET[3:0] and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
The data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles
before the end of the memory transaction. The following cases must be considered:
1. The memory asserts the WAIT signal aligned to NOE/NWE which toggles:
2. The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
then:
otherwise
where max_wait_assertion_time is the maximum time taken by the memory to assert
the WAIT signal once NEx/NOE/NWE is low.
Figure 469 and Figure 470 show the number of HCLK clock cycles that are added to the
memory access phase after WAIT is released by the asynchronous memory (independently
of the above cases).
Figure 469. Asynchronous wait during a read access waveforms
1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.
DATAST 4 HCLK×()max_wait_assertion_time+≥
max_wait_assertion_time address_phase hold_phase+>
DATAST 4 HCLK×()max_wait_assertion_time address_phase– hold_phase–()+≥
$>@
12(
+&/.
0HPRU\WUDQVDFWLRQ
'>@
1([
GDWDGULYHQE\PHPRU\
069
DGGUHVVSKDVH
GDWDVHWXSSKDVH
.7!)4
DONTCARE DONTCARE
To Next Page
Loading...
Need help?
General
