EasyManuals Logo

STMicroelectronics STM32F405 User Manual

STMicroelectronics STM32F405
1731 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #387 background imageLoading...
Page #387 background image
DocID018909 Rev 11 387/1731
RM0090 Interrupts and events
389
12.3.3 Rising trigger selection register (EXTI_RTSR)
Address offset: 0x08
Reset value: 0x0000 0000
Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines.
If a rising edge occurs on the external interrupt line while writing to the EXTI_RTSR register,
the pending bit is be set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
12.3.4 Falling trigger selection register (EXTI_FTSR)
Address offset: 0x0C
Reset value: 0x0000 0000
Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines.
If a falling edge occurs on the external interrupt line while writing to the EXTI_FTSR register,
the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
TR22 TR21 TR20 TR19 TR18 TR17 TR16
rw rw rw rw rw rw rw
1514131211109 8 7654321 0
TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 TRx: Rising trigger event configuration bit of line x
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
TR22 TR21 TR20 TR19 TR18 TR17 TR16
rw rw rw rw rw rw rw
1514131211109 8 7654321 0
TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 TRx: Falling trigger event configuration bit of line x
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the STMicroelectronics STM32F405 and is the answer not in the manual?

STMicroelectronics STM32F405 Specifications

General IconGeneral
BrandSTMicroelectronics
ModelSTM32F405
CategoryController
LanguageEnglish

Related product manuals