Flexible memory controller (FMC) RM0090
1590/1731 DocID018909 Rev 11
The FMC embeds two Write FIFOs: a Write Data FIFO with a 16x33-bit depth and a Write
Address FIFO with a 16x30-bit depth.
• The Write Data FIFO stores the AHB data to be written to the memory (up to 32 bits)
plus one bit for the AHB transfer (burst or not sequential mode)
• The Write Address FIFO stores the AHB address (up to 28 bits) plus the AHB data size
(up to 2 bits). When operating in burst mode, only the start address is stored except
when crossing a page boundary (for PSRAM and SDRAM). In this case, the AHB burst
is broken into two FIFO entries.
At startup the FMC pins must be configured by the user application. The FMC I/O pins which
are not used by the application can be used for other purposes.
The FMC registers that define the external device type and associated characteristics are
usually set at boot time and do not change until the next reset or power-up. However, the
settings can be changed at any time.
37.2 Block diagram
The FMC consists of five main blocks:
• The AHB interface (including the FMC configuration registers)
• The NOR Flash/PSRAM/SRAM controller
• The NAND Flash/PC Card controller
• The SDRAM controller
• The external device interface
The block diagram is shown in Figure 454.
To Next Page
Loading...
Need help?
General
