Flexible memory controller (FMC) RM0090
1654/1731 DocID018909 Rev 11
Figure 478. Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0)
During a write access or a Precharge command, the read FIFO is flushed and ready to be
filled with new data.
After the first read request, if the current access was not performed to a row boundary, the
SDRAM controller anticipates the next read access during the CAS latency period and the
RPIPE delay (if configured). This is done by incrementing the memory address. The
following condition must be met:
• RBURST control bit should be set to ‘1’ in the FMC_SDCR1 register.
-36
!("-ASTER
X
X
$ATA
$ATA
3$2!-
$EVICE
#!3
READREQUEST X
$ATA
LINES&)&/
!DD4AGREAD&)&/
$ATASTOREDIN&)&/
INADVANCEDURING
THE#!3LATENCYPERIOD
!DDRESSMATCHESWITH
ONEOFTHEADDRESSTAGS
&-#3$2!-#ONTROLLER
ND2EADACCESS 2EQUESTEDDATAWASPREVIOUSLYSTOREDINTHE&)&/
ST2EADACCESS2EQUESTEDDATAISNOTINTHE&)&/
!("-ASTER
X
X
$ATA
$ATA
3$2!-
$EVICE
#!3
READREQUEST X
$ATA
LINES&)&/
$ATAREADFROM&)&/
&-#3$2!-#ONTROLLER
!DD4AGREAD&)&/
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