STMicroelectronics STM32F405 User Manual

DocID018909 Rev 11 1291/1731
RM0090 USB on-the-go full-speed (OTG_FS)
1368
OTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx)
(x = 0..7, where x = Channel_number)
Address offset: 0x50C + (Channel_number × 0x20)
Reset value: 0x0000 0000
This register reflects the mask for each channel status described in the previous section.
Bit 2 Reserved, must be kept at reset value.
Bit 1 CHH: Channel halted
Indicates the transfer completed abnormally either because of any USB transaction error or
in response to disable request by the application.
Bit 0 XFRC: Transfer completed
Transfer completed normally without any errors.
313029282726252423222120191817161514131211109876543210
Reserved
DTERRM
FRMORM
BBERRM
TXERRM
NYET
ACKM NAKM
STALLM
Reserved
CHHM
XFRCM
rw rw rw rw rw rw rw rw rw rw
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 DTERRM: Data toggle error mask
0: Masked interrupt
1: Unmasked interrupt
Bit 9 FRMORM: Frame overrun mask
0: Masked interrupt
1: Unmasked interrupt
Bit 8 BBERRM: Babble error mask
0: Masked interrupt
1: Unmasked interrupt
Bit 7 TXERRM: Transaction error mask
0: Masked interrupt
1: Unmasked interrupt
Bit 6 NYET: response received interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 5 ACKM: ACK response received/transmitted interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 4 NAKM: NAK response received interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 3 STALLM: STALL response received interrupt mask
0: Masked interrupt
1: Unmasked interrupt

STMicroelectronics STM32F405 Specifications

General

Brand	STMicroelectronics
Model	STM32F405
Category	Controller
Language	English