DocID018909 Rev 11 135/1731
RM0090 Power controller (PWR)
149
In Stop mode, the following features can be selected by programming individual control bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 21.3 in Section 21: Independent watchdog (IWDG).
• Real-time clock (RTC): this is configured by the RTCEN bit in the Section 7.3.21: RCC
Backup domain control register (RCC_BDCR)
• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the
Section 7.3.22: RCC clock control & status register (RCC_CSR).
• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
RCC Backup domain control register (RCC_BDCR).
The ADC or DAC can also consume power during the Stop mode, unless they are disabled
before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit
in the DAC_CR register must both be written to 0.
Note: Before entering Stop mode, it is recommended to enable the clock security system (CSS)
feature to prevent external oscillator (HSE) failure from impacting the internal MCU
behavior.
Exiting Stop mode (STM32F42xxx and STM32F43xxx)
The Stop mode is exited according to Section : Exiting low-power mode.
Refer to Table 29 for more details on how to exit Stop mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is
selected as system clock.
If the Under-drive mode was enabled, it is automatically disabled after exiting Stop mode.
When the voltage regulator operates in low-power or low voltage mode, an additional
startup delay is incurred when waking up from Stop mode. By keeping the internal regulator
ON during Stop mode, the consumption is higher although the startup time is reduced.
When the voltage regulator operates in Under-drive mode, an additional startup delay is
induced when waking up from Stop mode.
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