STMicroelectronics STM32F405 User Manual

USB on-the-go high-speed (OTG_HS) RM0090
1436/1731 DocID018909 Rev 11
OTG_HS device OUT endpoint common interrupt mask register
(OTG_HS_DOEPMSK)
Address offset: 0x814
Reset value: 0x0000 0000
This register works with each of the Device OUT endpoint interrupt (OTG_HS_DOEPINTx)
registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint
interrupt for a specific status in the OTG_HS_DOEPINTx register can be masked by writing
into the corresponding bit in this register. Status bits are masked by default.
313029282726252423222120191817161514131211109876543210
Reserved
BOIM
OPEM
Reserved
B2BSTUP
Reserved
OTEPDM
STUPM
Reserved
EPDM
XFRCM
rw rw rw rw rw rw rw
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 BOIM: BNA interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 8 OPEM: OUT packet error mask
0: Masked interrupt
1: Unmasked interrupt
Bit 7 Reserved, must be kept at reset value.
Bit 6 B2BSTUP: Back-to-back SETUP packets received mask
Applies to control OUT endpoints only.
0: Masked interrupt
1: Unmasked interrupt
Bit 5 Reserved, must be kept at reset value.
Bit 4 OTEPDM: OUT token received when endpoint disabled mask
Applies to control OUT endpoints only.
0: Masked interrupt
1: Unmasked interrupt
Bit 3 STUPM: SETUP phase done mask
Applies to control endpoints only.
0: Masked interrupt
1: Unmasked interrupt
Bit 2 Reserved, must be kept at reset value.
Bit 1 EPDM: Endpoint disabled interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 0 XFRCM: Transfer completed interrupt mask
0: Masked interrupt
1: Unmasked interrupt

STMicroelectronics STM32F405 Specifications

General

Brand	STMicroelectronics
Model	STM32F405
Category	Controller
Language	English