STMicroelectronics STM32F405 User Manual

USB on-the-go high-speed (OTG_HS) RM0090
1450/1731 DocID018909 Rev 11
OTG_HS device endpoint-x interrupt register (OTG_HS_DIEPINTx) (x = 0..7,
where x = Endpoint_number)
Address offset: 0x908 + (Endpoint_number × 0x20)
Reset value: 0x0000 0080
This register indicates the status of an endpoint with respect to USB- and AHB-related
events. It is shown in Figure 412. The application must read this register when the IN
endpoints interrupt bit of the Core interrupt register (IEPINT in OTG_HS_GINTSTS) is set.
Before the application can read this register, it must first read the device all endpoints
interrupt (OTG_HS_DAINT) register to get the exact endpoint number for the device
endpoint-x interrupt register. The application must clear the appropriate bit in this register to
clear the corresponding bits in the OTG_HS_DAINT and OTG_HS_GINTSTS registers.
313029282726252423222120191817161514131211109876543210
Reserved
NAK
BERR
PKTDRPSTS
Reserved
BNA
TXFIFOUDRN
TXFE
INEPNE
Reserved
ITTXFE
TOC
Reserved
EPDISD
XFRC
r
rc_
w1
/rw
rc_
w1
rc_
w1
rc_
w1
rc_
w1
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 NAK: NAK interrupt
The core generates this interrupt when a NAK is transmitted or received by the device. In
case of isochronous IN endpoints the interrupt gets generated when a zero length packet is
transmitted due to unavailability of data in the Tx FIFO.
Bit 12 BERR: Babble error interrupt
Bit 11 PKTDRPSTS: Packet dropped status
This bit indicates to the application that an ISOC OUT packet has been dropped. This bit
does not have an associated mask bit and does not generate an interrupt.
Bit10 Reserved, must be kept at reset value.
Bit 9 BNA: Buffer not available interrupt
The core generates this interrupt when the descriptor accessed is not ready for the Core to
process, such as host busy or DMA done.
Bit 8 TXFIFOUDRN: Transmit Fifo Underrun (TxfifoUndrn) The core generates this interrupt when it
detects a transmit FIFO underrun condition for this endpoint.
Dependency: This interrupt is valid only when Thresholding is enabled
Bit 7 TXFE: Transmit FIFO empty
This interrupt is asserted when the TxFIFO for this endpoint is either half or completely
empty. The half or completely empty status is determined by the TxFIFO empty level bit in
the Core AHB configuration register (TXFELVL bit in OTG_HS_GAHBCFG).

STMicroelectronics STM32F405 Specifications

General

Brand	STMicroelectronics
Model	STM32F405
Category	Controller
Language	English